In Z80 memory read cycle is three T cycles, but, 2nd cycle only does "WAIT", and it appears timing would work with just two cycles unless the "WAIT" does something important. What is the reason memory read cycle is three T cycles?
The second cycle holds the requested address and control signals; it also samples WAIT in case a pause is being requested.
So it acts to give the component being addressed enough time to respond — you can [almost*] pick a processor clock speed based on the arithmetic that however many microseconds your RAM/etc needs to respond to a read or write should dictate the length of three clock cycles. Having that dictate two rather than three doesn’t make a huge difference.
* at least if the opcode read part of an M1 weren’t two cycles long. Some machines — including those confirming to the MSX standard — stretch the M1 read to three via WAIT in order to regularise it.