The MIPS architecture was introduced in 1981
Are you sure? To my information the first MIPS implementation was of 1985 with the R2000. Of course, the project did start before (in 1981), but so did others.
It is my understanding that VLIW architectures which also have an exposed pipeline, came later. Is that true?
As far as I can tell, yes.
Was MIPS really the first one?
Not really. For (modern) microprocessors Berkeley RISC I (the foundation of later SPARC) was 2-3 years ahead of MIPS, as their first working chips came in 1982. Berkeley RISC did not only coin the name RISC (and vanished somewhat behind after it became the standard term), but also featured a branch delay slot exposing the pipeline when branches were about. Here the compiler (or programmer) would place the last instruction to be done before a branch is taken after that branch.
But then there are minis, especially the IBM 801 (*1), which was defined in 1976. It had its first working implementation in 1978, first commercial usage in 1980 and first single-chip implementation (as ROMP) in 1981 (*2). Looking at their 1976 overview paper shows that they already incorporated almost every aspect of what got 'invented' half a decade later as RISC - including a separate set of branch instructions, called branch and execute (*3), where the next instruction in sequence after a branch will be executed anyway - today called a branch delay slot.
As of my understanding that makes the 801 implementation of 1980 the first.
*1 - It's debatable if that architecture really is a mini, as it is not only very /370ish, but also has been used as microcode engine for /370 implementations.
*2 - Fodder for what-if-freaks: What if IBM had used in 1981 their own 32 bit ROMP instead of Intel's 8088 for their PC (while also making the chip available to other manufacturers) :))
*3 - By having two sets of branch instructions they even avoided the need of inserting a NOP if there was no usable instruction - like with two successive branches. In reality it was more like a bit in the branch opcode telling whether the next instruction is executed or a virtual NOP is inserted.