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In this video from AT&T about Unix is a circuit design tool displayed that is claimed to be based on YACC (timestamped link).

Does anyone have information about this tool?

Like:

  • Documentation
  • Which projects were realized with this?
  • Source code, if possible

To me it appears like a predecessor to hardware description languages like Verilog or VHDL.

Googling showed up nothing that really resembles this tool. They mention a name but

  1. I don't understand the word properly (L-Gen? Elgen? Algen? Elgin?)
  2. Googling variations of this word also didn't help

edit

The answers so far mention a "Circuit Design Language" (CDL) that is also a tool for hardware design but not what I'm searching for. While CDL appears to be for describing wiring on a circuit board, the "L-Gen" tool describes apparently actual behavior of the logic.

A still image of the video showing the syntax of this language:

still image of the video showing the syntax of this language

Transcription of this still image:

NAME adder

LEFT in1, in2
BOT carryin
TOP carryout
RIGHT output

carryout = in1 in2 | in1 carryin | in2 carryin
output = in1 ^ in2 ^ carryin

Also, there is a "Unix Circuit Design System" of which I'm unsure about. Link: https://www.tuhs.org/Archive/Applications/Circuit_Design/

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    Most likely the name is L-GEN or LGEN, short for Layout Generator.
    – Raffzahn
    Commented Jan 29, 2023 at 19:04
  • There are several compnies named Elgin. Here is one.elginpowersolutions.com Commented Jan 29, 2023 at 19:57
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    There's a brief mention of Steve Johnson and VLSI work on the second page of archive.org/details/a_research_unix_reader (nicer OCR: cs.dartmouth.edu/~doug/reader.pdf). More than that there are frequent references to "UNIX Circuit Design System" including some details in section 4.3 that might be a more general lead to track down "l-gen" specifically.
    – natevw
    Commented Jan 30, 2023 at 22:32
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    That "Research UNIX Reader" cites (v7 pages 60-63) specifically, i.e. the seventh edition of The Unix Programmers manual presumedly volume 1. Unfortunately I haven't been able to find any PDF scans of the paper copy's volume one and the automated re-constructions at plan9.io/7thEdMan seem to be missing the CDL section.
    – natevw
    Commented Jan 30, 2023 at 23:05
  • Interesting question! I was considering asking this exact same thing 2 weeks ago, after re-watching the UNIX documentary. Interesting to read your response from Steve Johnson, and that you really went to the bottom with what "L-Gen" actually was.
    – BipedalJoe
    Commented Feb 24, 2023 at 22:28

3 Answers 3

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I can't find any "L-gen" specifically, but expanding from my comments on the question:

There's a brief mention of Steve Johnson and VLSI work on the second page of the "Research UNIX Reader" which can be browsed at https://archive.org/details/a_research_unix_reader (nicer OCR: https://cs.dartmouth.edu/~doug/reader.pdf). But more specifically than that there are frequent references to "UNIX Circuit Design System" throughout, including these details in section 4.3:

CDL (v7 pages 60-63)

Although most users do not encounter the UNIX Circuit Design System, it has long stood as an important application in the lab. Originated by Sandy Fraser and extended by Steve Bourne, Joe Condon, and Andrew Hume, UCDS handles circuits expressed in a common design language, cdl. It includes programs to create descriptions using interactive graphics, to lay out boards automatically, to check circuits for consistency, to guide wire-wrap machines, to specify combinational circuits and optimize them for programmed logic arrays (Chesson and Thompson). Without UCDS, significant inventions like Datakit, the 5620 Blit terminal, or the Belle chess machine would never hav e been built. UCDS appeared in only one manual, v7.

Unfortunately I haven't been able to find any PDF scans of the paper copy of volume one of that seventh edition of the Unix Programmer's Manual and the re-constructions at https://plan9.io/7thEdMan seem to be missing the CDL/UCDS section.

Searching for UCDS generally does turn up some manpages and such (under "V10"… so maybe the Research Reader predates a later edition that re-included the content?) for instance:

And there also was a 2015 forum thread that can be found at https[:]//www.unix.com/unix-and-linux-applications/263202-unix-circuit-design-system.html (spammy mirror site but some great background!) that points to two things:

In the contents of that file I have not found any references to a "gen" utility specifically, but there are some components named L-draw and L-poly!

There's a README [link directly downloads!] along side the archived ucds.cpio.gz that mentions:

I have found a distribution dated May 6, 1981 which maps to the 3rd version of the system.

So maybe there was indeed an "L-gen" at some point but was not yet/anymore in that release? I haven't read through the system documentation much at all and you may be able to match more of it to the video (or perhaps it was a different system entirely? but that seems less likely…).

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    Another potentially-relevant newsgroup thread about UCDS in a better archive: minnie.tuhs.org/pipermail/tuhs/2016-January/008026.html. And red-gate.com/simple-talk/opinion/geek-of-the-week/… is an interview with Johnson including a lot of YACC talk but doesn't mention VLSI/circuit much in the transcript itself.
    – natevw
    Commented Jan 31, 2023 at 0:10
  • Though not the software I asked for, it is still interesting. Apparently, this CDL language has another purpose than this "L-Gen" tool. While "L-Gen" appears to describe behavior of digital logic, "CDL" seems to describe the wiring on a board. Commented Jan 31, 2023 at 4:51
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    @ChristianDreier Yeah, the Verilog/VHDL angle is more interesting to me than just the general PCB layout stuff too! It looks like the "Unix Heritage Society" mailinglist at minnie.tuhs.org/cgi-bin/mailman/listinfo/tuhs is still active, maybe you could ask there and contrast the VLSI stuff you're seeing in the video with the UCDS stuff in their earlier minnie.tuhs.org/pipermail/tuhs/2016-January/008022.html thread?
    – natevw
    Commented Jan 31, 2023 at 20:41
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    "And perhaps maybe back then there was less of a distinction? Was making a mask for the ICs of that era considered just a constrained special case of generating a layout for TTL wiring at the physically larger PCB scale?" Possible, but I don't think so in this case. Additionally to the different purposes, the syntax as shown in the CDL documentation is very different to the "L-Gen" syntax as shown in the video. Commented Feb 1, 2023 at 12:04
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    @ChristianDreier Ah yes, there's a note about subscribing on the page I linked: "If you really want to subscribe to this list, [web search for one of the admins by name], and send him an e-mail asking to be subscribed to the TUHS list." as their spam prevention strategy.
    – natevw
    Commented Feb 2, 2023 at 4:50
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Unfortunately, it appears that there is really not much information about this peace of software out there. I asked the question in the TUHS mailing list and got even in touch with Steve Johnson himself (the guy who presented this software in the video).

It seems that this digital logic design language was part of a toolchain for integrated circuit design. This particular IC design toolchain seems to be only used for a course by Carver Mead.

Without some access to some AT&T software archive from 40 years ago (if it even still exists and contains this particular software) this may the only information available.

Below is the outline that Steve Johnson wrote to answer my question (emphasize mine):

The Bell Labs Mead Conway Course

Steve Johnson

In the early 1980’s, semiconductor technology was a very hot topic. At that time I was a department head and recruited at CalTech, where Carver Mead taught a class that allowed students to design nMOS chips and get them fabricated and then test the hardware. My boss, Sandy Fraser, had a lot of hardware experience, and many of us were curious to see what this new chip technology could make possible. After some negotiation, Carver agreed to visit the labs for 6 weeks and teach the class. Sandy pulled some strings and negotiated some aid from the AT&T chip makers. We would design a wafer with multiple different designs, and then the wafer would be sliced apart and each of us would get a few (3-5) chips they designed.

Having written the portable C compiler, and also one of the more enthusiastic supporters of this visit, I found myself “nominated” to write the software to support the design. We had just got our first VAX computer, which seemed to be powerful enough to support a dozen or so designers. I had about six weeks to throw together the software to support the chip design class.

To our surprise, there were roughly 30 people who signed up for the class. So, what kind of design should we provide.

The Mead/Conway “method” involved laying out the chip by hand following certain design rules. There were three kinds of wires: red, green, and black. The red and green wires were special: if a red wire crossed over a green wire, it made a transistor. The black wires carried the power and some of the data signals. In addition to the transistors, there were Vias – these allowed signals to cross between the red, green and black layers. The whole circuit was included in a “box” made up of pads, where the circuit would be connected to the pins of the fabricated chip.

There were also design rules. Transistors cannot be to close to other transistors or vias. To make logic circuits we needed to provide voltage and ground using the black wires. The whole circuit was designed on graph paper.

It quickly became clear to me that the design language should, as much as possible, hide the design rules so we could concentrate on the geometry. So the design language allowed you to define transistors and vias, and connect the wires to one of the four sides of the transistors or vias or pads. I don’t remember the exact syntax, but the design was a series of statements. Some statements defined names of transistors or vias or pads, without saying how they were connected. Then the heart of the language was doing the interconnections. The active elements had connection points U, D, L or R (for up, down, left, right). If V was a via, we might connect it to a transistor T by writing something like

T.RU = V.D

Which connected the right port of the transistor T with a wire that goes to the right and then up, and is connected to the down port of the via. Then the program would determine from the design rules how long the wire needed to go to the right and then upwards to hit V.

The design language also allowed you to design functional blocks like adders and treat them the same way as the builtin basic elements.

The design compiler became an exercise in finding the smallest layout that satisfies all the design rules. There were a variety of quirks that needed to be handled, especially regarding power and ground.

When transcribing a design with a few hundred wires it was remarkably easy to confuse left and right or up and down when describing the wire. This led to a cycle that could not be satisfied. To salvage something, hopefully, when there was a cycle, I deleted one of the constraints in the cycle, and tried again. Unfortunately, if the cycle had, say, 6 constraints I had less than a 20% chance of removing the bad one. So a large design with a single flaw could collapse into a murky mudball of elements with occasional wires and transistors sticking out of it. It was most demoralizing.

To add to the problems, when our VAX was delivered, apparently at some point something rolled over one of the cables, creating an intermittent fault. So for the first two weeks the VAX would take a very long time to get through all the designs. A frantic week’s work allowed me to package the design rule checker to draw a map of part of the circuit in 24x80 characters. You could zoom in to the site of the design rule error with a few keystrokes. It quickly became the preferred way to design. I remember giving a talk at MIT about the language and the design rule checker that was well received, but I doubt that it was recorded.

We produced, I think, 5 multiproject chips, roughly 2 a year. A sixth try was a failure: I had changed the checker to describe the elements by its center rather than the edges, which sped up the checker quite a bit. But when the design went to fab, the guy who usually checked the design for sanity was unavailable and the flaw was missed.

Some very interesting chips were produced in the course. Dave Ditzel implemented some ideas in silicon that later showed up in the AT&T Hobbit chip. There were also several network chips. For the third chip, I implemented a real silicon compiler. You could write a logic expression and it would compile it and produce output that could be used in the design. I generated a circuit that could take 16 binary inputs and produce the signals to drive five numerical outputs—a binary to decimal converter. The logic was complicated, but the program laid it out and the chip worked.

There were two reasons why the Silicon impulse petered out, in my opinion. One was, we didn’t have a good way to install the chips into any of the computers running Unix. And, if we had managed to do it, the chip would have to have some notion of which process it should respond to — it got complicated…

For me personally, I realized that the next step would be to dive into the physics of the system, and I had just accepted a transfer to the AT&T computer company spinoff, managing the language products for System V. This included the portable C compiler, the first commercial C++ compiler, Ada, FORTRAN and Pascal, and a debugger

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  • If it was used for the famous Mead/Conway course, potentially the book references it or has code samples. There's also plenty of other historical information about that course.
    – dirkt
    Commented Feb 25, 2023 at 13:08
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Only marginally related, but maybe interesting:

The paper "Circuit Design Aids" by A.G. Fraser, available for example in UNIX System Readings and Applications, Volume 1, (1987) AT&T Bell Labs starting on p. 323, describes a collection of tools similar to the one shown in the video, but for board layout, not for the integrated circuit systems themselves.

So writing these kinds of tools had a tradition at Bell Labs, including using a graphics terminal.

According from the description in the video, YACC was only used to write a parser for the description language (which is a natural and obvious thing to do, I have used YACC myself back then to write a quick parser for domain specific languages). So that was a very small part of the overall system.

And yes, it does look like a precursor to Verilog and VHDL, but again, writing those kinds of tools is a very natural thing to do and already had a tradition in Unix. It's the standardization and wide adoption that made Verilog and VHDL important.

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  • Indeed only marginally related. But the section about circuit design was a good and very interesting read. Commented Jan 31, 2023 at 4:36

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