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I have a question about the Z80 interrupt handling. This processor has 3 modes: 0, 1, and 2.

Modes 0 and 2 are supposed to fetch something from the data bus, and a protocol exists to inform the requesting device that it is time to produce such a piece of information.

Mode 1 does not accept data from the external device.
I would like to know if this mode will still produce the same interrupt ACK protocol used in modes 0 and 2. That is: starting the new M1 cycle with IORQ asserted instead of MREQ.

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1 Answer 1

Reset to default
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Z80 response in IM1 to an external interrupt is basically identical (apart from the trigger and RST address) to what happens in the NMI:

The CPU simply ignores the data bus during the next M1 cycle (even if /MREQ and /RD are asserted through that cycle) and executes a restart to address 38h (similar to a 66h in NMI). You can use the cycle diagram for the NMI in the Z80 interrupt documentation (page 7) to understand that.

/IOREQ is not involved during that cycle.

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  • Not sure about that because on page 9 the text says: "Maskable Interrupt Mode 1. This maskable .... (see figure 3) ... Note that when doing programmed I/O the CPU will ignore any data put onto the data bus during the interrupt acknowledge cycle. Now figure 3 shows that in Mode 1 there is no acknowledge cycle; So, why is the text saying: "CPU will ignore any data on the bus during the interrupt acknowledge."? It seems that the figure says that this does not happen, whereas the text refers to it as if it is going to happen. Very confusing. Is there someone with a logic analyzer?
    – ozw1z5rd
    Feb 14 at 18:14
  • @ozw1z5rd: If memory serves, the Z80 will wiggle its control lines the same way in all three modes when responding to an interrupt, whether this action is described as fetching the first interrupt instruction, fetching an interrupt vector, or wiggling control lines for the fun of it.
    – supercat
    Feb 14 at 21:43
  • @ozw1z5rd I'm not sure why you're saying "Now figure 3 shows that in Mode 1 there is no acknowledge cycle;" - You should be looking at figure 4 to see what happens with the control lines. And obviously, there's nothing of interest to the CPU on the data lines, why should it not ignore that? You actually seem to be looking at a comletely different document?
    – tofro
    Feb 15 at 8:22
  • Concur with @tofro here. Figure 3 is a sequence diagram so so safely leave out stuff that has no effect - a box containing the text "ignore something inconsequential" is unlikely to be useful :-) What really bugs my OCDness is the mode 0 "breakout" to push PC but not to return. Instead it's part of the main sequence with a comment "for call or rst only". Why not be consistent?
    – paxdiablo
    Feb 21 at 6:43
  • Hey, I also just noticed it seems to only re-enable interrupts if it was a call or rst. That can't be right surely. Wouldn't that mean that injecting a non-call instruction would leave interrupts disabled?
    – paxdiablo
    Feb 21 at 8:01

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