Unlike the original Apple ][, the Apple IIGS was built from highly-integrated custom chips. Among these were the Mega II and the CYA (which, apparently stands for "Control Your Apple").

From what I have read, all the discrete logic that made up the original Apple ][, plus the various enhancements in the //e, were replicated fully by the Mega II chip. This would seem to provide the necessary electronics for controlling the Apple IIGS expansion bus and compatible cards. So, what is left for the CYA chip to control? How does the CYA chip serve as an arbiter for peripherals builtin to the motherboard?

Also, is there a programmer interface for dealing with the CYA, and does it give the expansion bus of the IIGS any additional capabilities not found in the //e?

  • A quick read of apple2online.com/web_documents/… suggests that the Mega II runs at 1Mhz, ensuring compatibility with all classic add-ons, whereas the CYA runs at 2.8Mhz, handling everything on the board. I guess it'd be responsible for showing things down when a Mega II access is required, but that's just a guess. Hopefully somebody can provide a proper answer.
    – Tommy
    Apr 9, 2017 at 1:06

1 Answer 1


The "Control Your Apple ASIC" (CYA) was part of the "Apple IIGS 1 MB" introduced in 1989, which had 1.125 MB of DRAM and twice the ROM space of previous IIGS models. The CYA was much the same as the "Fast Processor Interface IC" (FPI) that earlier IIGS models had instead, and much of the technical documentation refers to either of the chips as the FPI. The new 1 MB model had version 3 of the ROMs and so this model is sometimes known as the "ROM 3" version of the IIGS.

The CYA/FPI exists to solve two problems while maintaining high compatibility with earlier Apple II models: allowing the newer, faster CPU to actually run faster, and to provide addressing to a larger amount of memory. Compatibility required that all the peripheral functions run at the older 1 MHz bus speed, including DMA (Direct Memory Access) from peripheral controlers to memory, so allowing the 65C816 CPU to run at a faster clock wasn't straightforward.

Consider the lower left of the IIGS block diagram from the Hardware Reference:

IIGS Block Diagram

The dashed line separates two clocking regions: the Mega II region to the right, running at 1 MHz, and the FPI region to the left, running at a variety of rates, up to 2.8 MHz. The Mega II region has all the peripheral connections, while the FPI region has the CPU, the ROM, most of the RAM memory, and the memory expansion slot. (The Mega II region has 128KB of the RAM, which can be directly accessed by peripheral DMA at the standard 1MHz bus rate.)

The CYA/FPI chip is there to control the timing and memory addressing in the FPI region. As long as the CPU accesses only memory in that region, the CPU (and the rest of the region) can be clocked at full speed. When the CPU has to access a peripheral or the memory residing in the Mega II region, the FPI chip reduces the region clock to 1 MHz. One of the memory functions of the FPI is to provide "memory shadowing" of some of the memory in the Mega II region (used for instance for the video display memory). This allows reads to use the FPI copy at full speed; only writes have to access the Mega II region at the slow speed.

The details of the CYA/FPI functions are more complicated than this; if interested you might want to watch this KansasFest "Apple IIgs System Timing and the FPI" video.

  • Nice answer. So is it true that the CYA has NO programmable registers of soft switches associated with it?
    – Brian H
    Apr 10, 2017 at 16:16
  • 1
    @BrianH, the Hardware Reference describes a Shadow register and a Speed register for controlling memory and clock speed attributes of the FPI.
    – mgkrebbs
    Apr 10, 2017 at 22:27

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