How much extra die area did a CMOS CPU take?

Question

Starting in the late seventies, the microchip industry generally switched from NMOS to CMOS, primarily because CMOS circuits use less power, though they also have other advantages like more noise tolerance.

CMOS circuits were initially slower, but this problem was solved by the late seventies, leaving the only disadvantage of CMOS being the extra transistors required. I vaguely remember it amounting to something like one extra transistor per logic gate, trying to find out how much that amounts to in terms of extra chip area for early CPUs.

https://en.wikipedia.org/wiki/Transistor_count

6502 is 4,528 transistors the way they are counting there; by the same counting(?), 65C02 is 11,500. That's 2.54x the transistor count for the CMOS version. If you instead look at the figures for die area versus process technology, it's just a shade over 2x.

But the 65C02 is not simply a CMOS version; it also makes some enhancements to the instruction set. Small enhancements, I think, but I don't know exactly how small in terms of added transistors.

What about the 8085? NMOS version is listed as 6,500 transistors. How many transistors, and what die area, was the 80C85?

Answer 1

CMOS requires 2N MOSFETs for every N inputs. NMOS requires (N+1) MOSFETs for every N inputs. This is why the CMOS versions of common micros, like the 65C02, have roughly double the number of transistors of their NMOS versions.

So, at first glance, a CMOS design will require some multiple of die size of the NMOS version, roughly double. There are, of course, other considerations, but in general, packing density was lower for CMOS and this was the primary reason it was not widely used even after the speed issues had been solved.

CMOS always had lower energy use, and found widespread use in low-power situations like digital watches and similar roles through the 1970s, at the height of NMOS' popularity, but for complex systems like CPUs and memory devices, NMOS remained the preferred solution into the 1980s.

One can find widespread debate on the advantages and disadvantages through the 1970s and into the 1980s. For instance, let me quote a 1984 paper on the topic from Bell Labs:

In the past, the basic reasons for choosing nMOS technology in a certain application have been the higher packing density, the higher circuit speed, and simpler processing. On the other hand, CMOS has always been the leading candidate in applications where power considerations came into play. ... As shown in the table, the major drawback of CMOS circuits is that, they require more transistors than nMOS circuits.

The debate between NMOS and CMOS was particularly notable during the development of VLSI, which was also introducing new methodologies for design which were based on much more "generic" design rules than the earlier highly fab-specific systems. As the process became more generic, there was the realization that CMOS would ultimately be no more difficult to design.

At the same time, Moore's Law was continuing its unrelenting march. As the fabs started pushing into the 1 um node, the issues with power distribution and heat loads were coming to the fore. So while CMOS might require twice the die size (it didn't, but it could) at any given node, it was also the only practical way to move to smaller feature sizes, and at the same time the design of such a layout was no longer as onerous as it had been.

So as the market continued to march down the feature size path, there was a phase change where, for any given (design effort x transistors x feature size) you could fab the CMOS at a smaller die size. From that point on it was CMOS all the way down.

Answer 2

If you had parity equipment and nodes, the CMOS implementation would be physically smaller. The "weak pull up" was created by having "n" diffusion implant into your "p+" wafer to make the resistor. Sometimes you would make the resistor longer or shorter depending on what you wanted to drive as it just a passive element. (This was all before my time, but wrote this in 2016 revisiting the work done in 1979 for a CMOS voltage reference in 1978. 40-years later 2 of the authors were still quasi-active in the space and I met them we had discussed the "good old days" of non-self aligning CMOS for hours.)

Generally, CMOS is just much better than NMOS logic and the fabs were changing by leaps and bounds then. One change that helped density over just going to CMOS was the increase in metal layers and stackable vias between the metal layers. There's "pass gates" on the original 6502 bus that are nFETs, and this causes and issue when you "pull-up" as the devices go out of saturation as you hit subthreshold (graph here) as the current goes way down as the resistance goes up. These are hard on timing, so you'd make these larger.

You can see these design choices from pictures of the masks on visual6502.org

(note: also, be careful of "gate count" as it changes or sometimes is difficult to determine the actual meaning. No one ever really had a standard. Intel used to call an XOR a gate, and you make it with 8 transistors. And some trivia, at IEDM, samsung's 3nm had 2-pFINS and 3-nFINS to make an inverter. In analog, we'd say 5 but it was 1 as a logic gate for samsung. I know this is an extreme example, but I just don't know when things got weird.)

Answer 3

The size ratio between equivalent "conventional" NMOS and CMOS designs varies with the feature size. If feature sizes of an NMOS design are cut in half, the amount of power each passive full-up would need to dissipate would likely go down somewhat, but the substrate surface area available to carry away heat, and thus the heat dissipation ability, would drop likewise. During the 6502 era, the substrate area under passive pull-ups was large enough that no extra area was required to carry away the heat they generated, but if feature sizes were to shrink very much that would cease to be the case.

It is likely not coincidental that early CMOS versions of chips had comparable die areas to NMOS versions, despite smaller feature sizes. If CMOS versions of chips had been constructed with the same feature sizes as earlier NMOS versions, they would have been much larger because they required more logic circuitry to accomplish many tasks. In NMOS, if one needs an N-input "NOR" gate, for almost any value of N, one can use one active transistor for each input, plus one passive pull-up on the output. Further, each input may be replaced with a two-input AND by replacing a transistor by a series string of two transistors, at a cost of a transistor for the extra input. Even three-input ANDs could be accommodated in this way, though one may need to use somewhat larger transistors to ensure that the output could switch quickly. Because all of the active transistors or pairs/triples thereof would be in parallel, circuit speed won't be appreciably affected by the number of inputs being NOR'ed together. Putting more than two transistors in series will degrade performance, making large NAND gates impractical, but most designs can be tailored to use more NOR gates than NANDs.

In CMOS, constructing a NAND gate of any size requires wiring active pull-down transistors similar to how they would be wired in NMOS, but also constructing a pull-up network with a topology similar to the pull-down network that would result if all NAND and NOR gates were swapped, and likewise the AND/OR gates on their inputs. In simple numeric terms, this means that at minimum, the number of transistors (plus pullups) for a gate with a total of N inputs will go from N+1 to 2N, but things are often worse than that. In NMOS, something like an 8-input or even 32-input NOR gate would be no problem, but in CMOS, the pull-up network for a single 8-input or 32-input NOR gate would require a series string of 8 or 32 transistors in series. Because a series string that long would drive its output very slowly, a CMOS design would need to use a cascaded sequence of gates (e.g. three NOR gates of 2-3 inputs each, driving a 3-input NAND gate, driving an optional inverter depending upon the desired output polarity).

Things may get even worse for CMOS if one considers that some arrangements of NAND and NOR gates that share inputs can be realized using fewer transistors than would seem to be required. For example, not (AB or CD or EBC or EAD) can be realized using five transistors in an H-shaped arrangement with AB and CD as the legs and E as the crossbar, but the inverse of that would not be amenable to such treatment. I haven't examined the 6502's BCD circuitry in any detail, but I suspect strongly that it uses some such constructs, and that the only way to efficiently handle BCD in CMOS is to split the addition and BCD correction into two separate steps.