CMOS requires 2N MOSFETs for every N inputs. NMOS requires (N+1) MOSFETs for every N inputs. This is why the CMOS versions of common micros, like the 65C02, have roughly double the number of transistors of their NMOS versions.
So, at first glance, a CMOS design will require some multiple of die size of the NMOS version, roughly double. There are, of course, other considerations, but in general, packing density was lower for CMOS and this was the primary reason it was not widely used even after the speed issues had been solved.
CMOS always had lower energy use, and found widespread use in low-power situations like digital watches and similar roles through the 1970s, at the height of NMOS' popularity, but for complex systems like CPUs and memory devices, NMOS remained the preferred solution into the 1980s.
One can find widespread debate on the advantages and disadvantages through the 1970s and into the 1980s. For instance, let me quote a 1984 paper on the topic from Bell Labs:
In the past, the basic reasons for choosing nMOS technology in a certain application have been the higher packing density, the higher circuit speed, and simpler processing. On the other hand, CMOS has always been the leading candidate in applications where power considerations came into play.
As shown in the table, the major drawback of CMOS circuits is that, they require more transistors than nMOS circuits.
The debate between NMOS and CMOS was particularly notable during the development of VLSI, which was also introducing new methodologies for design which were based on much more "generic" design rules than the earlier highly fab-specific systems. As the process became more generic, there was the realization that CMOS would ultimately be no more difficult to design.
At the same time, Moore's Law was continuing its unrelenting march. As the fabs started pushing into the 1 um node, the issues with power distribution and heat loads were coming to the fore. So while CMOS might require twice the die size (it didn't, but it could) at any given node, it was also the only practical way to move to smaller feature sizes, and at the same time the design of such a layout was no longer as onerous as it had been.
So as the market continued to march down the feature size path, there was a phase change where, for any given (design effort x transistors x feature size) you could fab the CMOS at a smaller die size. From that point on it was CMOS all the way down.