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I think even in the 1990s it wouldn't have been a problem to build a 4GHz clock generator.

Increase a transistor here and a resistor there and the clock rate will go up.

(I know there was DECT in the early 1990s and it had a frequency of 1900MHz in Europe. I only mention this to show building the clock generator was probably not the problem.)

So I wonder why exactly the frequency was so low compared to modern 4GHz CPUs.

I found an AMD 1998 CPU list and an Intel 1998 CPU list. The fastest in these two lists are the Intel Pentium III Xeon 500MHz engineering samples. But those are not serial models and most are around 300MHz.

Why didn't they have 4, 3 or at least 2 GHz?

Maybe it's because of the transistor size, RAM speed, heat, speed of light, ... I really dont know!

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    Radios have existed with higher frequencies than 1.9GHz since way before the 90s, so obviously clocks aren’t a problem, and they weren’t when CPUs ran at less than 1MHz... Apr 22, 2023 at 16:25
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    no power transistor in the Ghz range uses silicon, even today. A radio reciever needs only passive components at the carrier frequncy. Comparing mobile phone amplifiers using GaAs transistors with silicon devices intended for mass production is silly.
    – camelccc
    Apr 22, 2023 at 18:18
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    I don't remember thinking that desktop computers were slow in the 1990s. They sure were one **** of a lot faster than desktop computers we used back in the 1980s. Apr 22, 2023 at 20:59
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    @RonJohn Well, some experts at a high-profile processor company in the late 1990s seems to have though in a similar way than the OP, and created an x86 design to replace the Intel Pentium III that should run at way higher clocks by having very simple pipeline steps. The target was to hit 6GHz to 7GHz some years later. After loosing lots of market share to the competitor that had a more power efficient design, especially at idle, that design was finally abandoned and replaced by the Intel Core microarchitecture, a modernized Pentium III design. (I enjoy bashing the Pentium 4...) Apr 23, 2023 at 0:29
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    as a rough analogy, putting a bigger gastank and larger fuel injectors on a cheap car doesn't turn it into a racecar, it just floods the engine with more gas than it can handle
    – eps
    Apr 23, 2023 at 23:26

8 Answers 8

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As an extremely simplistic approximation, frequency is related to the size of transistors.

Smaller transistors and wire interconnects have smaller capacitance. Which makes them able to toggle faster and draw less power.

There used to be a quite direct relation, now it's far more complex :

https://en.wikipedia.org/wiki/Dennard_scaling

High frequency is also useful only with more complex architectures. There is no need to have a 4GHz CPU if all performance is lost accessing memory. So you need caches, pipelining, speculative Out Of Order execution... and millions of transistors.

Some exotic technologies such as ECL or sapphire could be a bit ahead of the curve and were used in old supercomputers (for example CRAY), with the price of horrendeous power draw, but now, nothing is better than CMOS.

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    Back in the day of the 8 bit computers, memory was commonly as fast as the CPU. The instruction length necessary to specify which memory location was needed was the slowdown. Apr 22, 2023 at 18:26
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    To summarize: computers are systems, and each piece of a system must work in harmony with all of the other pieces at a cost people will pay.
    – RonJohn
    Apr 22, 2023 at 20:22
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    The point about memory was also compounded by how comparatively register starved the at the time dominant CPU architecture for desktop systems was (x86 CPUs only have 8 GPRs in protected mode), which meant that RAM speed was a more significant factor for those systems than it was for something like a Sun workstation system of the same era (with it’s nice SPARC chip with 32 GPRs and fancy register-window based scoping that meant that simple functions didn’t even have to hit memory for data or temporary storage at all). Apr 24, 2023 at 1:19
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    I don't think anyone would describe Prime minicomputers as "supercomputers", but they used ECL in the 70s and early 80s too. CMOS was the new-fangled slow (but low power) technology (except that you can shrink CMOS to get higher speed, but if you do the same to ECL it cooks itself). Apr 24, 2023 at 8:29
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    @RonJohn : indeed, too many people forget this aspect. Many relatively modern inventions were introduced relatively late because there wasn't a market from them earlier. It's not because people in earlier times were too stupid to come up with the idea, it's because it wasn't economically viable. The first fax was sent in the 1860's, yet didn't become widespread until almost a century later.
    – vsz
    Apr 25, 2023 at 6:31
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A MOSFET transistor has a switching time that's related to the size of the transistors.

Basically the gate forms a capacitor with the substrate, and you have to load and unload the capacitor so the electric field can switch the rest of the transistor.

Now if you just increase the clock, the gate will only be half loaded or half unloaded, or in other words, your circuit isn't working properly.

So it's this characteristic that determines the maximal clock rate (together with other things like clock propagation).

The capacitance depends on the size of gate. Transistors have become smaller and smaller (and you get additional effects when you get really small, e.g. heat transfer is starting to become a problem). So in the 90s, with larger transistors than today, you had lower maximum clock rates, and in the 80s, even lower ones.

There are other factors that determine the maximal clock rate, like the technology used, so at every time you had outliers that used exotic more expensive technology to get higher clocks speeds (the Cray is a good example), but still the mainstream clock rate is what it is.

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Even during World War II, a 1GHz oscillator would not have been impractical to build. Indeed, the Soviets used an oscillator operating at around that frequency immediately after World war II in order to operate a tiny covert listening device in the US Embassy in Moscow.

There's an important difference, though, between an oscillator operating at 1GHz and a computer operating at 1GHz. A typical 1GHz oscillator would have been constructed using a passive resonant circuit along with some active electronics which are only able to add a tiny amount of energy during each cycle. The passive resonant circuit will repeatedly convert energy between two forms (e.g. an electric field in a capacitor and a magnetic field in an inductor), so the active circuitry will only need to add enough energy to make up for energy lost or radiated from the passive circuit. When starting up the oscillator, it would probably have had to oscillate for many cycles to reach full amplitude, and the passive resonant circuit was probably strong enough relative to the strength of the drive circuitry that even stopping it instantly would have been difficult.

In order for computers to operate at 1GHz, however, it's necessary to have active switching elements that can take a circuit that's "at rest", fully switch its state, and have the circuit be at rest in the other state, all within a fraction of a nanosecond. That requires the ability to switch much more power than would be necessary merely to maintain oscillation.

While many other factors would limit practical CPU speeds to a fraction of the fastest practical speeds for simplier things like counters, the most important factor is probably the fact that most of the "work" done within each oscillation is done by the passive circuit elements.

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Just producing a steady frequency doesn't mean one also has components working at those frequencies for other purpose than (analogue) generation, amplification, shaping and detection - like the sequential logic operation needed for a CPU.

Rudolf Kühnhold, at the Kriegsmarine Versuchsanstalt, did build as early as 1933 transmitters operating at 2.22 GHz - it still took a 'few' more decades until logic would operate at such speeds.

Other Answers already provided good lead of technical reasons about this. But we are often way too much focused on the technological side of development, ignoring that it always happen within a business framework: Every development needs an adequate market - especially if it comes with huge upfront investments. Or more direct:

There is no reason to build the fastest CPU possible for mass market devices.
All worth to invest for a good sale is one a tad faster than the competition.


The 1990s are a story of good enough and Intel's hubris in overestimating their ability to twist licence contracts, underestimating the ability to scale their own designs as well what progress competition may yield. Also, with the late 1990s you picked roughly the moment in time when the MHz-Race started to gain speed. So let's do a (not so) quick look at the time line:

Licencing CPU designs was a major part of Intel's business since 8080 days, but already in the early 1980s it became obvious that not only the PC market will be the biggest single CPU market, but as well that their licencees did make nice profits by delivering better performance at lower prices. While Intel provided the 80286 at 5 to 12 MHz, AMD provided versions up to 25 MHz. Making pressing the turbo-button worthwhile :)

So when introducing the i386 in 1985, they stated that existing agreements would not cover this brand new chip, so no schematics were shared, Intel wanted to be the sole proprietor of the new 386 world (*1). What followed was a long sequence of law suits, reverse engineering, more law suits, technological advance, more law suits, and Intel loosing the lead in every step over and over again.

After not coming to an agreement AMD for one started to reverse-engineered the 386 while also suing Intel for upholding the existing licence as the 386 was an obvious incremental improvement to the 286.

Intel did manage to slow that project down for considerable time, but in 1991 introduced their Am386 at 40 MHz - Intel only ever had the 386 increased to 33 MHz. While Intel had in the mean time (1989) introduced the 486, it was quite expensive while not being that much faster. An Am386-40 would compare quite well to an i486-25 at lower CPU and board cost. So AMD snapped a large part of the strong 386 market plus eating into low end 486 sales (especially all 486-SX).

Intel countered with another law suit - in addition to one running about the 287. And lowered their 486 prices considerable. When the 287 one was decided in 1993, the jury not only granted the rights for the FPU, but everything up to and including the 486.

Which came perfect for AMD as they just finished their Am486, a fully compatible one (including the original Intel micro code). Right from the start AMD offered the same speed grades as Intel plus a 40 MHz bus version.

What followed was a short race with double and tripple clocked 486 versions where AMD again collected a good part of the market.

But that law suite also did set the bar for Intel to 'finally' get free of competition as it limited the existing licences to the 486, excluding any Pentium or later. This lead directly to the next overestimate of their abilities: By assuming that their Pentium was so superior, in 1992 they planned a roadmap consisting of a Pentium slowly creeping up from 60 to 166 MHz over the next 6 years. They were so confident that the P5 design will rule the market,that they even started to develop the independent (and forgotten) PentiumPro (aka P6) line, reserved for expensive high end workstations and servers.

Except, the AMD's 486 performed way better than expected. Tripple and quad clocked improved 486 designs (*2) turned lower end Pentium (60..90) into letter weights. Same performance, less than half the CPU price and cheaper boards (since still 486) made them a great seller and cash cow for AMD.

Intels rescue was the Pentium MMX - a side project developed in Israel (*3) - which combined P5 and P6 architectures into one being considerable faster than either (*4).

Since they couldn't clone the Pentium, AMD did come up with their own design, the K5. While quite comparable in integer performance to Pentium at same or higher speed, it failed on FP performance - and didn't scale as well (*5)

At that point we reached 1997 and Intel tried to break free with the Pentium II. Leaving the Socket 7 for Slot 1, where CPU and separate Cache were placed as on a PCB as a processor Module (*6). Having such a great idea and product, Intel felt again that they would for sure rule the market for the next 5+ years. Roadmaps of that time showed the Pentium II slowly going from 233 to 400 MHz over the next 4 years (1997..2000). What a cosy world that will be ...

... except, a month before Intel introduced the Pentium II, AMD brought the K6, on par with the PII at similar clock, scaling as good,but still only needing a Socket 7 (Pentium type) motherboard. The K6 and it's follow up K6-2, K6-III did eat deep into Intels market share. Intel tried to counter with the Celeron to gain back the low end, but never compete always with lower performance at the same price point.

And then it was 1999 (*7) and the Athlon blasted everything Intel could deliver. And it even scaled better than Pentium II or Pentium III. It was not only when the point when the MHz race really took off, but also the first time that a CPU company raced itself. Unlike Intel, who tried twice to slowly squeeze out the market, AMD raised the mark in just 9 month from 500 MHz in June 1999 over 700 MHz in Oktober, to 1 GHz in March of 2000. All while lowering the price.

The rest is ... (*8)


So, long story short:

With the historic exception of a few years between 1999 and 2003, being just a bit faster is what sells your product and competition is what drives that spiral.


*1 - IIRC only IBM was granted a licence.

*2 - Like the final 5x86

*3 - Israel is kind of famous to develop 'unimportant' CPU variant that happen to change the course - starting with the 8088 :))

*4 - No, that is not about brighter colours and better sounds, btu real speed up. After all, noone had a use case for the MMX part at the time.

*5 - Lucky for intel, as the Pentium MMX also didn't scale well.

*6 - Essentially the same idea that got reborn recently with AMD Ryzen's chiplets.

*7 - And right after the questions sample date :)

*8 - We all know History doesn't repeat, but then there came AMD Threadripper and Ryzen :))

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    "Intel's hubris in underestimating the ability to scale their own designs" - something doesn't match there ...
    – davidbak
    Apr 23, 2023 at 1:03
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    @davidbak their hubris in assuming they had the market locked up and the competition would never beat them led them to underestimate what they could do with their designs because they didn't think they needed to do much better.
    – eps
    Apr 23, 2023 at 23:29
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    @davidbak Well, I'm open to a better wording, but to my understanding it names a know-it-all and I'm-better-than-everyone-else attitude - which is exactly what Intel showed by believing not only that the 486 was a dead end, ignoring the simple idea of cranking up clock speed, followed by assuming that noone would be able beat their new design, which led to making very detailed plans about long term world domination (well, at least CPU market domination) twice - and failing twice in a row.
    – Raffzahn
    Apr 23, 2023 at 23:39
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    I didn't get that at all - thanks for the explanation! (I usually associate hubris with expectations that are greater than you can achieve.)
    – davidbak
    Apr 24, 2023 at 0:41
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    @davidbak Isn't that exactly what happened? They thought of themself as outperforming everyone else, but jumped way too low? Let me add a few story points :))
    – Raffzahn
    Apr 24, 2023 at 0:50
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Data in this answer is from memory, as I tossed out my paper copies of Microprocessor Report years ago. They may be off slightly, but hopefully not dramatically.

Other answers have already touched on the importance of transistor switching speeds for processor operating frequency, as well as the limiting factor of memory access speed, both DRAM and SRAM.

There is an additional, micro architectural, factor that plays a role: pipeline depth. More pipeline stages means less logic depth and thus less delay per pipeline stage, allowing the processor to operate at a higher frequency. In practical terms, running a longer, faster pipeline requires additional transistors. For example, performance loss from branch mispredicts increases with pipeline length, requiring more elaborate branch prediction mechanism. Also, larger caches requiring more transistors will be needed.

An interesting case study how far better manufacturing technology can push a processor design is IBM's PowerPC 750, which had a 4-stage pipeline for integer instructions. It debuted at 266 MHz in 1997 and reached 1.1 GHz in its last revision, the 750GX, in early 2004.

However, CPUs with longer pipelines started to get designed, so at the end of the 1990s we had AMD K6 with a 6-stage pipeline reaching 550 MHz, then at the start of the millennium the Athlon processor with a 10-stage pipeline reaching 1 GHz, followed by the Opteron with a 12-stage pipeline, allowing frequencies to climb further.

Some CPU engineering teams took this to extremes, with Intel delivering CPUs based on the Prescott microarchitecture with its 31-state pipeline in Q1/2004 operating at a whopping 3.4 GHz, with final models in Q3/2005 reaching 3.8 GHz. They even planned a follow-on architecture code-named Tejas with around 50 pipeline stages operating at 5-7 GHz; the effort was abandoned.

What had been "overlooked", but became all too clear at this stage, is that as pipelines get very deep, power consumption increases faster than processor speed, and the PC world wasn't ready for 250W CPUs at that point. The problem is that data has to be retrieved from flip-flops at the start of every pipeline stage, flows through a few levels of logic and promptly needs to be stored again. Lots of energy is needed to move data in and out of storage.

Modelling revealed that "optimal" performance per watt is achieved around 15±2 pipeline stages and many CPU designs approached this in the 2005 to 2015 time frame. Now Moore's Law has come to the end of its applicable range, but with consumers requiring still more performance, pipeline lengths for high-performance CPUs have climbed a bit to about 15-20 stages in the latest microarchitectures, allowing operating frequencies (albeit for short periods of time) of up to 6 GHz

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    Modern Microprocessors A 90-Minute Guide! covers some of the history of things that limit CPU frequency, including power density becoming a major limiting factor in the early 2000s. (As you say, hitting the "power wall" was what sunk Pentium 4, preventing it from scaling up to those planned clock speeds above 5 GHz. It took multiple decades of improvements in power-gating and process improvements to get to 5GHz, although that's in modern "brainiac" CPUs that also aim to get a lot of work done per clock cycle, not just high clocks) Apr 24, 2023 at 0:40
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    @PeterCordes The "power wall" has also become more flexible due to real-time monitoring of power draw and die temperature plus fine-grained control of clock frequency. What used to be a 20% design margin in the chips of old has been whittled down to a few percent now, the balance being exploited through the use of sophisticated dynamic clock boosting mechanisms in both CPUs and GPUs. The power cooling wall has also been moved to > 100W for PC CPUs, whereas the PPC 750 @ 266 MHz used something like 8W max., 6W typical.
    – njuffa
    Apr 24, 2023 at 2:34
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A single 4 GHz transistor is easy. A 20 transistor chain running at 4 GHz needs 80 GHz transistors.

The maximum speed that CPU can run at is determined by the critical path. This is the longest path from one register to next register which stabilize to correct result before the next clock edge. These Berkeley course notes have a good explanation of it.

In a radio receiver, only a few transistors are involved in handling the analog RF signal. It is enough if the propagation delay of a single transistor is somewhere around 100 picoseconds.

In CPU design, there is a tradeoff between how much you can do in a single clock cycle and how long that clock cycle must be. Typically multiplication and addition are the longest operations that are executed in a single pipeline stage. These operations are needed for many purposes, such as incrementing program counter and calculating memory addresses, so they are often the bottleneck for performance.

A 32-bit carry-lookahead adder has a critical path length of about 10 gates or around 20 transistors. Therefore using a 4 GHz clock, where a clock cycle lasts 250 ps, requires each transistor to stabilize in less than 12 ps.

In modern CPUs this is achieved by making the transistors very small in physical dimensions, so that only a few electrons need to move to change the electric field. This has required a lot of development in microchip manufacturing to be able to create such small details.

In general, raising the operating voltage and current of transistors speeds them up. But there is a limit in both heating and in diminishing returns. The 1990s technology could probably have manufactured a 1-bit CPU running at 4 GHz, but a 32-bit CPU running at 500 MHz was more useful for practical purposes.

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  • While there would be a significant time between being able to design e.g. an arbitrary-pulse counter that could operate at 1GHz and a CPU that would operate at that speed, there's a bigger difference between oscillator speeds and gate speeds. Consider that radios were operating a tens if not hundreds of MHz even before the invention of the vacuum tube.
    – supercat
    Apr 24, 2023 at 14:57
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    For CPU-architecture novices, the "one register to next register" critical path length is one pipeline stage. The registers being discussed here are the buffers between stages, not architectural "cpu registers" like EAX. Apr 26, 2023 at 7:39
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    Making a simple ALU instruction like add or adc run in 1 cycle instead of needing to break it up into 2 stages is a big deal, because it's not rare for one instruction to use the result of the previous, and an in-order pipeline can't do anything to hide latencies of true dependencies. Also would cost many transistors for the pipeline stage registers, and those flip-flops themselves would have some latency. But pentium 4 did it anyway (and ran the ALUs at double the clock speed to compensate, giving 4/clock throughput for integer add instructions.) Apr 26, 2023 at 7:41
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Transistors have a frequency limit based on their dimensions which affects parasitic capacitances. It's not easy to construct a tiny microtransistors on a silicon wafer, let alone the millions or billions that are required for a processor.

Knowing how a smaller transistor will behave is not the same as actually knowing how to construct a smaller transistor, or being able to do so reliably, or being able to do in quantity. You do not just decide that you will build transistors smaller and then build them smaller. Each technology node that reduces feature size takes research and development of both the process the equipment. It's not doing the same thing again, just smaller transistors and more of them. That would be like assuming that all you had to do to get humans to Mars was to just build everything the in the Apollo program bigger.

Attempting to tackle in one fell swoop the accumulated challenges that took decades of incremental development and refinement by jumping from when jumping from 100MHz of a 486 straight to the 3GHz of an Pentium 4 would inevitably lead to failure. At best you would develop the intermediary sizes nodes along the way without commercializing them which would starve the project of funding.

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Those Intel and AMD processors were limited by the available heat budget. They could have made them go faster, which would consume more power, which would make them overheat and die.

People did 'overclock' them, with extra cooling, but that took them out of guarantee: Intel and AMD simply couldn't guarantee that they would work at higher internal power levels, and lacked the ability to make effective processors that used less power.

Subsequently, the Pentium IV approached this problem by using a simple internal RISC structure, which enabled them to go faster with less power. Ultimately, that was not a successful architecture, and the next generation used a different approach to reducing temperature, while de-emphasizing clock speed: the 'clock speed' of modern processors is almost entirely an "equivalent number" having no relationship to the actual clocking of most transistors in the processor.

The 80286 was almost entirely limited by the bus speed: they could have made a much faster 80286, with a good heatsink, but most of the mother-board designers lacked the ability to design a faster motherboard. At 8088 speeds you can consider differential track lengths and track coupling, but you mostly don't have to. When MB speed was boosted from 5 to 64MHz, old designs didn't work. By the time of the Pentium II, MB designers had caught up with memory speed, and the PII/PIII packages allowed good heat dissipation and good bus speed, and were not limited by MB speed. P4 was able to drop the special package and daughter board, because it had tighter MB and heatsink specification.

MB speed continued to increase, driven by lower memory voltage allowing faster memory speed. And processor 'clock' speed has increased, permitted by lower voltage, better voltage regulation, and sophisticated power management.

At present, CPU 'clock' speed remains mostly decoupled from MB speed, and constrained by power budget.

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