This should be an easy one but stick with me here. I think that page 46 of the ISA Bus Specification by Intel shows it's read on the rising edge. Intro to the ISA bus by Mark Sokos seems to agree on line 413. Or is it read on some other clock edge?
Looking at this guy's design:
IC10, a GAL, asserts the '245 bus transceiver /OE only when /IORD or /IOWR is asserted. (I can post the logic equations if necessary) If my assumption is correct about when data is read/written to the bus, how would this work? If data is sampled on either edge of /IORD or /IOWR, this is a problem as the '245s /OE is changing state on that edge.
If this isn't correct, what the correct time to assert /OE on an IDE bus transceiver besides when either IDE chip select is asserted?
EDIT: a published Compaq schematic for an I/O card I believe asserts '245 /OE without regard to /IORD or /IOWR (referenced by the very helpful Michael Karcher here on retro SE), which further confuses me.