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Hope this is ok here. This seems to be the place with the real hardware experts. As some of you may recall, I've been trying to get a 44 pin IDE SSD module working on a retro IDE interface. The SSD datasheet is here: https://www.alldatasheet.com/datasheet-pdf/pdf/330168/TRANSCEND/TS128MDOM44H-S.html

I tried using a standard 44 to 40 adapter but things act weird. An AMI BIOS 286 detected phantom COM ports and the floppy change line didn't work, and a 486 using MR BIOS wouldn't even POST, complaining about a DMA failure. I discovered this SSD likes to drive its data lines when the /IORD is asserted even without a chip select asserted, so it stomps on everything else.

Now, this is occurring on systems that use a super I/O card based on a Holtek HT6550A. These cards don't appear to be very old relative to IDE (I think from about 1995), but they don't do much for IDE other than decode the two IDE chip selects. The schematic in the datasheet seems to be pretty close to the actual card implementation. These cards do not use bus transceivers or buffering and instead connect the data lines, A0-A2, /IORD, /IOWR, etc. directly to the ISA bus, hence the reason the SSD can screw things up. This doesn't occur on a 386 and 586 with an integrated IDE port and 74x245 parts near the port. I think this tells me there isn't a fundamental incompatibility working on old systems, considering the 386 is a 1992 Compaq (and the 4GB SSD works with the Compaq's original BIOS!).

As I have a quantity of these SSDs and several old computers to use them in, I began work on a custom PCB that would add bus transceivers and hopefully fix the problem, and also be a nice compact adapter.

It's intended to be roughly the size of a credit card and plug directly into an IDE port, providing a place to plug in the SSD, and also a 40 pin header for a slave device. Power will be from a regular power supply drive connector. The GAL code is below. I have used extra pins to buffer signals from the ISA bus and also so I have access to those should I need to include those in the logic later. It's nice to know I can change the logic at any time.

/* *************** INPUT PINS *********************/
PIN   2 = IOWR; /*                                 */ 
PIN   3 = IORD; /*                                 */ 
PIN   4 = IO16; /*                                 */ 
PIN   5 = A1; /*                                 */ 
PIN   6 = A2; /*                                 */ 
PIN   7 = A0; /*                                 */ 
PIN   8 = CS1; /*                                 */ 
PIN   9 = CS0; /*                                 */ 


/* *************** OUTPUT PINS *********************/
PIN    12 = BUF_A0; /*                                 */ 
PIN    13 = BUF_A2; /*                                 */ 
PIN    14 = BUF_A1; /*                                 */ 
PIN    15 = BUF_IOWR; /*                                 */ 
PIN    16 = BUF_IORD; /*                                 */ 
PIN    17 = IDEHI; /*                                 */ 
PIN    18 = IDE3F7; /*                                 */ 
PIN    19 = IDELO; /*                                 */ 

!IDELO = !CS0 & !IORD 
    # !CS0 & !IOWR 
    # !CS1 & !IORD & !A0 & A1 & A2
    # !CS1 & !IOWR & !A0 & A1 & A2;

!IDEHI = !CS0 & !IORD & !IO16 
    # !CS0 & !IOWR & !IO16;

!IDE3F7 = !CS1 & !IORD & A0 & A1 & A2;
BUF_A0 = A0;
BUF_A1 = A1;
BUF_A2 = A2;
BUF_IOWR = IOWR;
BUF_IORD = IORD;

I have breadboarded this (solderless breadboard), but the results are very inconsistent. The Compaq 386 is perfectly happy accessing the SSD through it. The 286 (with XT-IDE) and 486 are pickier. I have changed things on the breadboard over time, including going from discrete logic to the GAL and trying 74HC and 74F parts, but right now it consistently detects the drive on POST, but won't get further than "Starting MS-DOS". I can boot from a floppy and access C: with no issue, although drive corruption occurs very frequently. I can always partition and format it without error. If I can somehow get it to boot from the SSD, it freezes when running any .bat file (weird....weird).

My thought is the breadboarded circuit is bad enough from a signal quality standpoint and I need to move to trying this on a PCB.

Any thoughts on the circuit design (or anything else)? It seems fairly straightforward and low-risk. This will go on a 4 layer board with power and ground planes.

The schematic:

enter image description here

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    I think this is more an electronics question. You are trying to make a new modern adapter for connecting new modern and backwards incompatible CF cards with 44-pin IDE-alike interface to retro hardware. At least using HC type chips is wrong as these are TTL levels. The exact type of the GAL is missing too, it may be timing critical, but at least it should use TTL levels.
    – Justme
    May 2, 2023 at 6:23
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    Im wondering if you have hit the nail on the head Justme, mixing HC and TTL does need pullup resistors, and its not clear if the op has these
    – camelccc
    May 2, 2023 at 9:37
  • I think you have given me a good lead here. I was subconsciously aware of the TTL-CMOS issue but didn't seriously consider it. One type of input on the SSD is rated for minimum 4V for a logic high, and I doubt this is occurring consistently. Thank you for pointing this out.
    – eesz34
    May 2, 2023 at 11:11
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    OK, if you don't have pullup resistors, the value will need to be chosen to allow for the capacitance of the cmos input to get the required rise time, as ttl can not source current at all, only sink it. This leads to surprisingly small values. I suspect (this is a guess) that the newer boards may have buffered ttl, hence your board works on some boards and not others. A ttl bufffer ic may be a better bet here.
    – camelccc
    May 2, 2023 at 13:15
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    Would the close voters mind explaining what details are missing here? May 3, 2023 at 16:17

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