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After an MC68000 processor is released from reset, it fetches the initial stack pointer and initial program counter from the vector table at addresses 0-3 (for the SP) and addresses 4-7 (for the PC).

Since 68k instructions need to be two-byte aligned, the PC in a 68k is not supposed to be set to an odd address. During normal operation, after initial vector fetch, jumping to an odd address would cause an address error exception.

Does an address error occur if an odd address is fetched from the initial PC vector after reset, or does the MC68000 have a different behavior in this case?

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    If an exception is triggered during the exception processing for a reset, the system enters a halted state. I don't know, however, whether the act of loading an odd address into the program counter would be viewed as triggering an address error while processing the reset, or if the address error would be treated as having occurred as soon as reset processing was complete. Likewise if PC was valid but the stack pointer was odd, I don't know if the system would halt immediately or only when something tried to access the stack.
    – supercat
    Commented May 19, 2023 at 19:58
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    @supercat, yes, double bus faults are easy and well documented but the OP's question is asking something different. I couldn't immediately see anything in the Motorola MC68000 User Manual (9th edition) on a superficial skim-through. It'll be important for answerers to stick to this aspect of this MPU and not write a big answer on what something else they do know all about does, which happens quite often on SE :-)
    – TonyM
    Commented May 19, 2023 at 21:03
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    @TonyM: If one tries to do a JMP @A0 when A0 holds an odd number, is the program-counter value that gets pushed for the trap the address of the JMP instruction or the value that was in A0? If the latter, then I would expect the on-reset scenario to load PC with an odd value, exit reset handling, and trap when it attempts to fetch the first instruction. If the former, then I would think it more likely that the condition would cause an immediate halt. Interesting question, since the scenario could easily arise when powering up a system with a blank EEPROM.
    – supercat
    Commented May 19, 2023 at 21:16
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    @supercat, it is indeed an interesting one. For what it's worth (and I don't think it's worth much), the EASy68K simulator appears to force the reset vector's bit 0 to 0 then jump there. So setting the reset vector to $00001001 made it jump to $00001000. But I don't trust the simulator to give the definitive answer for the real MC68000 silicon, nor an HDL version of it. With the best of intentions, the authors could well have filled in any obscure knowledge gaps like this sort of thing with their reasonable interpretation of what it should do.
    – TonyM
    Commented May 19, 2023 at 22:10
  • I assume the processor raises the address exception not when jumping to an odd address, but rather when reading an instruction from an odd address - therefore, the reset should happen successfully, and the very first instruction should throw the error. Commented May 22, 2023 at 15:01

1 Answer 1

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TL;DR:

There is no reason to add additional hardware to test especially for reset, or any vector at all for an odd address as that test is done by default with the first access using that PC, more so, as doing that access may also reveal all kinds of external errors (abort / BERR).


Manual Wrangling

As assumed, the processor will be going into HALT state, as per section 5.3.10 of the April 1983 data sheet (ADI-814-R4):

enter image description here

(Emphasis mine)

Workings are based on two basic mechanisms:

Address error exceptions occur when the processor attempts to access [...] an instruction at an odd address.

That is what an odd PC value in vector 1 will of course produce as soon as the first access is done.

[I]f an address error occurs during the exception processing for[...] reset, the processor is halted.

Which is the natural reaction if there is no way around - aka a double fault.

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    Your first sentence would suggest that there would be no need to test the PC address until after the reset processing was done and the system was processing the first instruction in normal fashion. On the other hand, it would probably have been considered desirable to ensure that if the address-error vector held an odd address, the system wouldn't simply generate endless stores to descending addresses.
    – supercat
    Commented May 20, 2023 at 16:05

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