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I'm trying to understand how the RST 7.5 interrupt circuit works in the Explorer 85 level A, since in the i8085 the address jumped is located in 003CH (for level A there is no memory mapped here), but the monitor handles this interrupt in the address F03CH. Could somebody please explain me which part of the circuit does this?

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  • 1
    Looks much like partial decoding, doesn't it?
    – Raffzahn
    Jun 23, 2023 at 20:46

1 Answer 1

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TL;DR:

During Reset and Interrupt handling the ROM is accessed for one instruction fetch instead of RAM (*1)


The Explorer/85 is, as it's schematic show, a very BASIC 8085 system using the full shortcuts of it's bus system to attach a

  • 8155 providing
    • 256 Bytes RAM
      • at F800h plus
    • Timer and I/O and a -8355/8755 with
    • 2 KiB of Mask Programmed ROM (8355) or EPROM (8755)
      • at F000h and as well
    • some I/O

Looking at the schematics, as well as the assembly manual (and peeking over the board) reveals that there is dedicated logic to fetch one instruction from the 8755 ROM. For all practical purpose this is like mapping it down from F800h to 0000h. Thus when the CPU starts to fetch the RST 7.5 vector from 003Ch, it gets the bytes located otherwise at F03Ch..F03Eh, which contain a jump into RAM at F8A6 (C3 A6 F8), a location within RAM so it can be redirected. By default it's set to forward to F024h, the monitors Warm start.

The logic used can be found in the upper right corner of the schematic, where a three input NAND (*2) at position U115 detects a reset/restart situation (Signal /BOOT ACTIVE) which in turn activates the chip select for the ROM, independent of address decoding (NAND at position U107).


*1 - For versions other than Level A additional signals are included to fetch from RAM instead, depending on situation.

*2 - The schematic draws it as OR with inverted inputs, which is equivalent. Doing so eases reading - despite looking odd to today's readers.

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