# How could the Intel 4004 address 640 bytes if it was only 4-bit?

I am reading Computer Organization and Architecture, 10th ed. by William Stallings and I found this on page 26.

where it says the addressable memory of 4004 is 640 bytes.

But it appears that the Intel 4004 only had 4 pins for "MEMORY CONTROL OUTPUTS", which apparently was used to address memory location:

So how was it possible to address 640 bytes? Isn't the total addressable memory 2^n, where n is number of bits, therefore 2^4 = 16 bytes?

• How could it address more than 16 bytes if it was only 4 bits? For that matter how does an 8-bit 6502 or 8080 address 65536 bytes? Jul 4, 2023 at 21:59
• @Harper et al, in fairness, both the 6502 and 8080 have 16 address pins and 8 data pins, so they can access 64K address space of 256 values each without any trickery. The 4004 does not have 12 address pins or 8 data pins to do the same thing with 4K address space of 256 values, which is why it has to handle addresses and data 4 bits at a time. That's why this question was asked. Jul 5, 2023 at 5:04
• A similar trick is still done nowadays, AFAIK. The Intel i7 only has 32 pins but is a 64 bit processor. It transmits 32 bits on the rising edge and 32 bits on the falling edge. Jul 5, 2023 at 13:36
• I am reminded of the days I spent BBSing back in the 80's - when we learned that what you mean and what you type frequently come out different. It never hurts to think twice about how your comment might be misinterpreted and it never hurts to give someone the benefit of the doubt. Now, everyone get off my lawn. :-) Jul 7, 2023 at 19:05

There may only be four pins coming out from the chip but it allowed for more than sixteen values because it multiplexed 4n-bit values onto those four pins based on timing.

The instructions for accessing memory are a bit complex. For example, the following code will write the nybble value 7 into memory address 9 (of the currently selected bank, see below for details):

``````       ;; Use DCL with accumulator if you need to change bank.
;; First bank after reset is 0.

20 09  FIM P0, 9 ; set reg pair P0 (R0/1) to 09h.
21     SRC P0    ; set address bus location to pair 0.
D7     LDM 7     ; load 07h into the accumulator.
E0     WRM       ; write accumulator to address bus location.
``````

Now I wouldn't have thought this possible but that seems to be even lower level than "normal" assembly language :-)

It also provides a clue as to how things are done under the covers. For example, the timing diagrams for the i4004 show that the four-bit "packets" of each instruction are placed onto the data bus at different times in (stages of) the instruction cycle.

The `synch` line (on low to high transition) starts an instruction cycle and the two clocks `ϕ0` and `ϕ1` advance the stage of the instruction cycle after that, as per the following graphic:

The stages shown there are `A1-A3`, `M1-M2`, and `X1-X3`, and these account for the instruction address output to the ROM memory sub-system, instruction input from the ROM memory sub-system, and execution of the instruction:

• Four bits are written in each `A` stage to indicate the 12-bit address of the desired instruction. ROM select is forced high during this time since instructions cannot be retrieved from RAM (it's Harvard architecture).

• Four bits are read in each `M` stage to get an 8-bit instruction also with ROM selected (there are also two-byte instructions which defer execution until the next instruction cycle, when the second byte has been retrieved).

• Finally, the `X` stages are for executing the actual instruction, including reading or writing to I/O and RAM memory if need be (with similar multiplexing as instruction fetch).

As an aside, the i4001 chip was the ROM sub-system, and the RAM subsystem was formed with some number of i4002 chips, each holding 320 bits (though I seem to recall they both also provided some I/O capacity as well).

Each of the four RAM banks (selectable with pins `CM-RAM0-3` on the i4004) could contain four individual i4002 RAM chips (each with 320 bits).

Hence total RAM capacity was `4 x 4 x 320 = 5120` bits, equivalent to 640 8-bit bytes, as shown in the table from the question.

Note that this was a simple case where each `CM-RAMn` pin selected its bank (one of four). In this case, the `DCL` instruction would set one pin depending on those bits from the accumulator:

``````Bits  CM-RAM pin
----  ----------
000      0
001      1
010      2
100      3
``````

However, astute readers will now be wondering what happens if you set multiple bits in the accumulator. And, in fact, it turns out that something like `011` will set both `CM-RAM1` and `CM-RAM2`.

While this would cause an issue with the simple case (multiple banks may respond, leading to bus contention and possible data corruption), you could add a 3-to-8 decoder to `CM-RAM1-3` pins to effectively get eight banks, doubling the amount of RAM. The eight possible values of those three pins would select one of eight chip-select signals, each going to a different bank.

And I originally wondered why you couldn't use a 4-to-16 decoder to double memory again but I suspect the `CM-RAM0` pin is set only if all the others are clear, something easy enough to do with a few gates (so no way to select both `CM-RAM0` and `CM-RAM1` at the same time, for example).

• Do you happen to know how this multiplexing of 12 bits to 4 pins was done? Jul 4, 2023 at 8:03
• @DarkDust I wonder that too. Jul 4, 2023 at 8:21
• @DarkDust: added that detail, hopefully that's enough to aid understanding. Jul 4, 2023 at 9:47
• "that seems to be even lower level than "normal" assembly language." Yes. The 1970s microprocessors we think of as "really basic" actually have quite a bit of design effort to make them easier to program. For a really low-level instruction set, look at the DEC PDP-8, the first commercially successful minicomputer. Jul 4, 2023 at 14:03
• Ah, it really was lower-level, a bit like a writing the microcode layer of a later-class CPU. Jul 4, 2023 at 14:51

The 4004 used the data bus for both addresses and data. The memory control outputs were used for bank selection.

Here's how it works:

1. At the beginning of the instruction, the CPU raises `SYNC` to let all the memory chips know that it is at the start of an instruction.
2. The CPU places 12 bits of address in three blocks of 4 bits on the data bus. This takes three clock cycles, typically labelled A1, A2, A3. The address selects an 8 bit byte from up to 4KB of ROM.
3. The ROM sends back the 8 bit byte in two blocks of 4 bits using two clock cycles on the same data bus, labelled M1, M2. We have taken five clock cycles just to get the instruction.
4. The CPU executes the instruction over three clock cycles labelled X1, X2, X3.

Where it gets complicated is in reading or writing data. You may think "issue a load/store instruction" but it is not that simple. It takes several instructions to read or write data. Here's roughly how it gores:

1. Execute a `DCL` (designated command line) which uses the accumulator to select a RAM bank i.e. set one of the `CM-RAM` lines.

2. Execute an `SRC` (select register control) which places the content of a register pair (registers are 4 bit) in two blocks of 4 bits on the data bus during cycles X2, X3.

3. The next instruction tells the CPU and the ROM and RAM what to do next e.g. read or write data.

With the 4004, the RAM and ROM need to have some capacity for keeping track of state, which is somewhat weird and, I think, limiting.

Information sourced from the MCS-4 Users Manual.

• Why is the limit 640 bytes? Wouldn't 4 banks * 256 addresses give 1024 bytes of addressable memory?
– Mark
Jul 6, 2023 at 0:42
• @Mark, each 4002 RAM chip held 320 bits (four sections, each with 20 4-bit characters). Each of the four CR-RAM-(0-3) selectable banks of the 4004 allowed for four 4002 chips (two 4002-1 and two 4002-2). Hence there was a total of four banks by four chips by 320 bits available, giving a total of 5,120 bits. This is equivalent to 640 8-bit bytes. Jul 6, 2023 at 15:24

Both answers of paxdiablo and JeremyP are fine, but if you want a more practical view - though it uses the successor 4040 chip - the British magazine Practical Electronics had a 10 part constructional project from September 1977 through June 1978. It was something like a follow-up to its introductory series "microprocessors explained" that ran from March 1977 through August 1977. The project included a programmer and a UV-eraser for EPROMs. And - please, don't laugh - it was my first home "computer". You can find the issues of the magazine at worldradiohistory.com

• I was a PE subscriber from 1973, but don't remember this one. I built a Nascom 1 as my first computer. Jul 4, 2023 at 19:03
• Very strange grahamj42 as it was one of the first computer projects published in a magazine ... Jul 5, 2023 at 6:08
• I'm laughing, but in delight... thanks for sharing this! Jul 15, 2023 at 18:09
• My first home computer was a ZX80, so the chances of me laughing at someone else's choice are pretty much zero :-) Sep 4, 2023 at 23:05