There may only be four pins coming out from the chip but it allowed for more than sixteen values because it multiplexed 4n-bit values onto those four pins based on timing.
The instructions for accessing memory are a bit complex. For example, the following code will write the nybble value 7 into memory address 9 (of the currently selected bank, see below for details):
;; Use DCL with accumulator if you need to change bank.
;; First bank after reset is 0.
20 09 FIM P0, 9 ; set reg pair P0 (R0/1) to 09h.
21 SRC P0 ; set address bus location to pair 0.
D7 LDM 7 ; load 07h into the accumulator.
E0 WRM ; write accumulator to address bus location.
Now I wouldn't have thought this possible but that seems to be even lower level than "normal" assembly language :-)
It also provides a clue as to how things are done under the covers. For example, the timing diagrams for the i4004 show that the four-bit "packets" of each instruction are placed onto the data bus at different times in (stages of) the instruction cycle.
synch line (on low to high transition) starts an instruction cycle and the two clocks
ϕ1 advance the stage of the instruction cycle after that, as per the following graphic:
The stages shown there are
X1-X3, and these account for the instruction address output to the ROM memory sub-system, instruction input from the ROM memory sub-system, and execution of the instruction:
Four bits are written in each
A stage to indicate the 12-bit address of the desired instruction. ROM select is forced high during this time since instructions cannot be retrieved from RAM (it's Harvard architecture).
Four bits are read in each
M stage to get an 8-bit instruction also with ROM selected (there are also two-byte instructions which defer execution until the next instruction cycle, when the second byte has been retrieved).
X stages are for executing the actual instruction, including reading or writing to I/O and RAM memory if need be (with similar multiplexing as instruction fetch).
As an aside, the i4001 chip was the ROM sub-system, and the RAM subsystem was formed with some number of i4002 chips, each holding 320 bits (though I seem to recall they both also provided some I/O capacity as well).
Each of the four RAM banks (selectable with pins
CM-RAM0-3 on the i4004) could contain four individual i4002 RAM chips (each with 320 bits).
Hence total RAM capacity was
4 x 4 x 320 = 5120 bits, equivalent to 640 8-bit bytes, as shown in the table from the question.
Note that this was a simple case where each
CM-RAMn pin selected its bank (one of four). In this case, the
DCL instruction would set one pin depending on those bits from the accumulator:
Bits CM-RAM pin
However, astute readers will now be wondering what happens if you set multiple bits in the accumulator. And, in fact, it turns out that something like
011 will set both
While this would cause an issue with the simple case (multiple banks may respond, leading to bus contention and possible data corruption), you could add a 3-to-8 decoder to
CM-RAM1-3 pins to effectively get eight banks, doubling the amount of RAM. The eight possible values of those three pins would select one of eight chip-select signals, each going to a different bank.
And I originally wondered why you couldn't use a 4-to-16 decoder to double memory again but I suspect the
CM-RAM0 pin is set only if all the others are clear, something easy enough to do with a few gates (so no way to select both
CM-RAM1 at the same time, for example).