According to Computer Wars by Charles H Ferguson and Charles R Morris, page 40-41, an IBM researcher named Cocke in the early 70s built a RISC minicomputer called the ServiceFree (because it was meant to be simple enough to require little maintenance), that achieved extraordinary performance:

The ServiceFree was a small computer, potentially quite inexpensive, and screamingly fast. Cocke, who is cautious in the extreme about making claims, has reported that the ServiceFree ran at 80 MIPS – that's about fifty times faster than IBM's fastest mainframes at the time.

Leaving aside that the strength of a mainframe was more in its storage and bandwidth than sheer CPU speed, nonetheless, 80 MIPS in the mid-70s is an extraordinary claim indeed.

Did this actually happen? Was this machine real? I've tried a few Google searches, and not found any significant documentation on it. If it was real, did it actually achieve anything close to that performance figure? If so, how?

  • 6
    Remember: "MIPS" stands for "Meaningless Indication of Processor Speed".
    – Mark
    Commented Aug 11, 2023 at 3:32
  • Yes, but there are more formalized benchmarks (Dhrystone/Whetstone) also using the MIPS as a unit.... Commented Aug 15, 2023 at 20:33

2 Answers 2


This seems to be a mangled account of the IBM 801. The project was led by John Cocke. This started as a project for a computerised telephone switch, which needed a lot of instructions per second, but they didn't need to be complicated. So there was no microcode, no floating point, and few instructions acting directly on memory. It was a much simpler design than IBM's mainframes and could conceptually reach the required performance,

IBM abandoned the telephone switch project, but continued with the processor design, as it was promising. During the development, several RISC ideas were discovered, including compilers' preferences for simple instructions. It was also found that while naïve compiling with a simple instruction set produced larger programs than the same source compiled for S/370, optimising compilers could reduce that loss considerably.

The original 801 implementation was a 24-bit machine using two registers in each instruction and lacking virtual memory. The same ideas in a 32-bit, three-register-per-instruction architecture that supported virtual memory evolved into the IBM POWER architecture and PowerPC.

I'm not sure where the 80 MIPS figure in the quote came from. The 801 could not do that, but IBM POWER and PowerPC evolved far past that performance level.

  • Perhaps 80 MIPS was a corruption from 801 ? Faxes were a great source of noise-induced error back in 1993 when this book was published.
    – Criggie
    Commented Aug 11, 2023 at 4:10
  • 2
    @Criggie Saying that the ServiceFree ran at 80 MIPS reading a fax that mention ServiceFree and IBM 801 would require more than noise-induced errors.
    – apaderno
    Commented Aug 11, 2023 at 10:02

John Dallman already showed the 801 being the most likely one referred to. The 801 was indeed the ground breaking work Mr. Cocke was later recognized for. In addition it might be helpful to check the claim about speed in relation to mainframe and against what is known about the 801/RS6000/PowerPC line

Did the IBM ServiceFree really reach 80 MIPS in 1975?

First of, the switch project was cancelled in 1975 without ever creating a working machine. It took until 1980 to implement the first working 801.

Cocke, who is cautious in the extreme about making claims, has reported that the ServiceFree ran at 80 MIPS

Now that number does not correlate what is known.

  • The switch project was targeted for 'only' 12 MIPS execution, but no machine was build.
  • When the 801 was implemented for the first time in 1980 it ran at a clock rate of ~ 15 MHz, which would peak at 15 MIPS - if only single cycle instruction were used - real thruput might have been much less.
  • 1981 the first ROMP chipset was designed
  • 1986 brought the PC-RT, the first end user machine. Available with 6 to 12 MHz clock
  • 1990 the POWER1 was introduced with the RS/6000 line with up to 30 MHz
  • in 1993 the POWER1+ and POWER2 reached 62.5 MHz (later 71.5 MHz)
  • It wasn't until 1996 that the P2SC clocked at 120 MHz
  • In parallel the cooperation with Motorola produced the PowerPC line with the 601 being the first introduced in 1993. It had a different instruction set, but was the first to reach plain 80 MHz

To shorten the timeline:

  • In 1975 there was no machine of that structure
  • In 1980, 5 years later, implementatiton may have reached 15 MIPS
  • In 1986, 11 years later, it was a product
  • In 1996, 21 year later, it has reached/passed that 80 MIPS claim

– that's about fifty times faster than IBM's fastest mainframes at the time.

But even if it ran at 80 MIPS (which it did not), 50 times may work in relation to a mid range 1970s System /360, but not with mainframes in 1975. The 1972 IBM System/370 Model 168 already peaked close to 10 MIPS and averaged at 3 MIPS, while a 1977 3033 at least doubled the average. So lets make that 5 to 10 times, at most, not considering he less capable instruction set.

But it was RISC machine, thus by very definition needing more instructions to do the same as a CISC. If at all it would be fair to compare it to a mainframe's micro-program level. Which in fact is rather relevant as the 801 has many features to ease translation of /370 code (*1).

So no, 50 times does not work out as absolute number in relation to mainframes and even less when considering the nature of instructions.

*1 - Quite like the 8086 was made to resemble the 8080.

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