TL;DR: It's two chips in one
A memory manager/addressing unit and a streaming display engine (*1), each with their own dedicated data port. Splitting the structure into two unidirectional interfaces allowed simpler hardware structure, more flexible operation and higher speeds.
And speed this is about - hence also the dedicated video memory.
Why they didn't multiplexed everything on the same bus?
Jup, that could have worked, but might have made the chip more complex and run into speed issues. This becomes visible when looking at the structure presented in the block diagram:
(Taken from p.2-2 of the 1982 TMS9918 Data Manual)
This shows nicely the tight, streaming orientated read structure (red outline) separated from the more general control section. The upper works during display quite like a Motorola 6845 generating all timing while the lower gets fed the data fetched and turns them into pixels. Almost like two different chips with minimal interaction (*2).
That minimal interaction is what makes the chip go extremely fast for its time. For the second part, having its own unidirectional port takes out all timing consideration. It doesn't need to do any addressing and directional switching. It just streams whatever it gets fed.
The upper part on the other hand does all RAM timing for the second and inserts whatever writes it has - after all, its port is also unidirectional, so it's all about sequencing the various RAM access requests with a simple two-tier priority scheme: Streaming first, CPU second.
The streaming data is accessed via AD1..7/RAS/CAS, delivering its data on RD0..7 to the second unit. Likewise all CPU writes - which is the most common interaction the CPU has - are handled in full by the upper half using AD0..7/RAS/CAS/WR with no interaction or interference to the second unit.
This leaves only two interactions between those, and both are also unidirectional:
Forwarded addressing to fetch data (like char/sprite pointers)
Here the streaming part delivers a pointer to be added with some base and output in the next cycle.
The rarest case of all (*3); here a byte is read on the streaming side (when there is no picture) and placed into a communication buffer (*4)
Splitting the structure into two unidirectional interfaces allowed simpler hardware structure, more flexible operation and higher speeds.
Finally there is the side issue of simply following the basic split of Din/Dout of contemporary RAM. By doing so, there are fewer assumptions made about what RAM does with either, allowing the use of a greater variety.
*1 - Which in some way is more related to today's GPUs then other early video chips. The 9918 always generares each picture direct from memory structures, with each item read from video memory, modified by further reads into other structures and processed into a video out stream. Others, like the VIC reads character lines and modify them with on chip data.
*2 - A concept used by Motorola with their 6883 SAM/6847 VDG combination used in all SAM machines (CoCo, Dragen, etc.):
The main difference the 9118 makes is to pack all of that into one chip (including all buffers and secondary logic) while keeping the performance and simplicity of two dedicated units.
(Note, the 6847 can also be used on its own)
*3 - This includes the 99/4 where (as cost cutting measure) video memory is also used to store BASIC program and data. TI BASIC peaks at 50-100 instructions per second or about 1-2 per screen displayed. It's safe to assume an average BASIC instruction needing less than 30 bytes to be read, which means more than 99% of all access cycles will be for screen data - a clear reason to build such a streaming structure and have everything else be of secondary concern.
Any other machine (like MSX) will do even less reads.
*4 - Done in a prefetch manner, so sequential reads can perform reasonably fast.