Usually 8bit video chips interface with DRAM using:

  • an address bus for rows and columns,
  • a bidirectional data bus

in the case of 1bit DRAM data-in and data-out pins are shorted on the same data line.

The TMS9918 is different,

  • address and data-in are multiplexed on the same bus
  • data-out has its own bus

Why they didn't multiplexed everything on the same bus?

The saved pins could have been used for something else or to reduce the package cost.

  • Without looking at any detail, don't all chips have broadly three functions: something in - some process - something out? If the chip really can handle only one on each clock cycle, why worry about which? If the chip can handle more than one function in the same cycle, why restict it to choposing between in and out? Commented Aug 26, 2023 at 19:28

3 Answers 3


The TMS9918 has eight pins that combine "address out" and "data out" functions, while using another eight pins for "data in". Because typical 16Kx1 DRAM chips don't have an /OE (output enable) signal separate from /CAS (column address strobe), they start outputting data as soon as /CAS goes low, which would lead to a bus conflict if the TMS9918 was outputting an address at that time. While the TMS9918 could have used the same 8 pins to output data as it uses to read data, that would have required having intput/output circuitry on the eight data pins, in addition to the output-only circuitry on the eight address pins. The design they chose precludes use of the later-to-be-introduced 16Kx4 DRAMs (which have a separate output-enable control, but don't have separate data outputs) but avoids the need to include output circuitry on eight of the pins.

  • 1
    When /CAS goes low it takes a while before data is available (access time from CAS) and data out is high impedence. They could have used that time to put in high impedence the address drivers. web.archive.org/web/20181120132001/https://console5.com/… Commented Aug 25, 2023 at 15:03
  • @ValentinoMiazzo: The specified column address hold time is 55ns, and I don't see any guaranteed minimum time before a RAM chip starts outputting (not necessarily correct) data. If it were not possible to have eight separate readback pins, it might have been possible to connect the DRAM outputs to the address/data bus via ~2.2K resistors, so that as long as the TMS9918 was outputting its address it would "win", but after it floated its outputs it could see the incoming data, but making that work reliably would probably require slowing things down a bit compared with the present design.
    – supercat
    Commented Aug 25, 2023 at 15:18
  • @ValentinoMiazzo: Also, while the present design doesn't exploit this, having separate address and data wires would have allowed a design which uses two bytes of shape data per eight pixels to exploit page-mode addressing to improve memory bandwidth.
    – supercat
    Commented Aug 25, 2023 at 15:22
  • Yeah, that's why the TMS9118 is the kind of design that op was hoping for. Commented Aug 25, 2023 at 15:51
  • Found the 9118 variant of 9918 that uses 4bit DRAM chips. Thank you . Interestingly it continues to use 2 busses (this time one for data and one for addresses ) even if now OE is available on DRAM chips. I may create a new question just for the 9118. Commented Aug 26, 2023 at 13:48

Let's see the datasheet for 9918 first and see how the VDP to VRAM write sequence works.

enter image description here

Before the write cycle, the VRAM chips were all held in the READ mode (R/~W signal is held high by VDP). This means VRAM's data input pins becomes inactive hence will ignore the VDP's address output on the A/D bus, so that the VDP can put the address on the A/D bus and strobe it into VRAM chips. After that the VPD put data on the A/D bus, falling edge of R/~W will strobe the data into the VRAM.

If address is multiplexed with both data in and data out, then as @supercat points out, without OE pins, there will be a conflict no matter how the R/~W is set. If R/~W is high, then VRAM's data output conflicts with VDP's address output. If R/~W is low, then VRAM would grab the address that VDP has put onto the bus as data.

If you separate out address bus but multiplex data in with data out, then it will work but the data port are now bi-directional so becomes a bit more expensive. Same thing if address is multiplexed with data in.

Here's the connection diagram between the VDP and VRAM. enter image description here

  • Using a single 8-bit bus, bus conflicts could be eliminated on writes by asserting R/W before /CAS, since data is latched on the rising edge of /CAS or R/W, whichever happens first, rather than the falling edge. Reads would be the big problem, since it would be possible for a DRAM chip to start driving its data output (not necessarily with meaningful data) before all of the DRAM chips have latched the column address.
    – supercat
    Commented Aug 25, 2023 at 17:55

TL;DR: It's two chips in one

A memory manager/addressing unit and a streaming display engine (*1), each with their own dedicated data port. Splitting the structure into two unidirectional interfaces allowed simpler hardware structure, more flexible operation and higher speeds.

And speed this is about - hence also the dedicated video memory.

Why they didn't multiplexed everything on the same bus?

Jup, that could have worked, but might have made the chip more complex and run into speed issues. This becomes visible when looking at the structure presented in the block diagram:

enter image description here

(Taken from p.2-2 of the 1982 TMS9918 Data Manual)

This shows nicely the tight, streaming orientated read structure (red outline) separated from the more general control section. The upper works during display quite like a Motorola 6845 generating all timing while the lower gets fed the data fetched and turns them into pixels. Almost like two different chips with minimal interaction (*2).

That minimal interaction is what makes the chip go extremely fast for its time. For the second part, having its own unidirectional port takes out all timing consideration. It doesn't need to do any addressing and directional switching. It just streams whatever it gets fed.

The upper part on the other hand does all RAM timing for the second and inserts whatever writes it has - after all, its port is also unidirectional, so it's all about sequencing the various RAM access requests with a simple two-tier priority scheme: Streaming first, CPU second.

The streaming data is accessed via AD1..7/RAS/CAS, delivering its data on RD0..7 to the second unit. Likewise all CPU writes - which is the most common interaction the CPU has - are handled in full by the upper half using AD0..7/RAS/CAS/WR with no interaction or interference to the second unit.

This leaves only two interactions between those, and both are also unidirectional:

  • Forwarded addressing to fetch data (like char/sprite pointers)

    Here the streaming part delivers a pointer to be added with some base and output in the next cycle.

  • CPU read

    The rarest case of all (*3); here a byte is read on the streaming side (when there is no picture) and placed into a communication buffer (*4)

Bottom line: Splitting the structure into two unidirectional interfaces allowed simpler hardware structure, more flexible operation and higher speeds.

Finally there is the side issue of simply following the basic split of Din/Dout of contemporary RAM. By doing so, there are fewer assumptions made about what RAM does with either, allowing the use of a greater variety.

*1 - Which in some way is more related to today's GPUs then other early video chips. The 9918 always generares each picture direct from memory structures, with each item read from video memory, modified by further reads into other structures and processed into a video out stream. Others, like the VIC reads character lines and modify them with on chip data.

*2 - A concept used by Motorola with their 6883 SAM/6847 VDG combination used in all SAM machines (CoCo, Dragen, etc.):

enter image description here

The main difference the 9118 makes is to pack all of that into one chip (including all buffers and secondary logic) while keeping the performance and simplicity of two dedicated units.

(Note, the 6847 can also be used on its own)

*3 - This includes the 99/4 where (as cost cutting measure) video memory is also used to store BASIC program and data. TI BASIC peaks at 50-100 instructions per second or about 1-2 per screen displayed. It's safe to assume an average BASIC instruction needing less than 30 bytes to be read, which means more than 99% of all access cycles will be for screen data - a clear reason to build such a streaming structure and have everything else be of secondary concern.

Any other machine (like MSX) will do even less reads.

*4 - Done in a prefetch manner, so sequential reads can perform reasonably fast.

  • 1
    What you refer to as the two halves of the chip are pretty strongly connected since e.g. the selection of what addresses to use for sprite data fetches would be dependent upon sprite Y positions which were fetched from DRAM, and I think the main thing that makes it cheaper to send CPU data out the pins that are used for addresses is the fact that those pins already need output driver transistors, avoiding the need to add another eight pairs.
    – supercat
    Commented Aug 25, 2023 at 20:42
  • @supercat Check again, I didn't say they are not connected - which would be stupid - but that that connections are unidirectional, which includes the external data port. Saving drivers and time to switch is a resulting benefit from that unidirectional flow design, not reason or cause. Having that streaming doesn't eliminate the need for a second addressing but doesn't create it in the first place. So yeah, if you insist, you're mixing up cause and effect in your description.
    – Raffzahn
    Commented Aug 25, 2023 at 21:06
  • 1
    Your bold-faced TLDR implies a degree of partitioning which exists in some other video subsystems, but not really in the TMS9918. The memory-control half of the system needs to be connected to the read-data bus, and could send data there essentially as easily as to the address bus, save for the need to add eight pin drivers, without having to involve the other half of the chip in such action.
    – supercat
    Commented Aug 25, 2023 at 21:38
  • @supercat he controller part does not send data to the readbus - why at all? The only connection is for CPU initiated reading, which is, as mentioned done by a buffer - which again is unidirectional. Of course they are interacting, but in a strict hierarchy and unidirectional flow.
    – Raffzahn
    Commented Aug 26, 2023 at 13:39
  • 1
    @Raffzahn interesting the analysis of what is goings-on inside the chip. I'm interested in your statement: "Yep, that could have worked," . How? Using external circuitry? Assuming a minimum undocumented t_cac? Commented Aug 26, 2023 at 13:41

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