The contents of processor registers of a PDP-11/05, etc were available at UNIBUS memory addresses and it was possible to execute a small test program just in the processor registers without accessing any main memory i.e. not in core or MOS memory modules.

Is there an online reference or can somebody provide that code here?

  • Do you mean that the program itself was stored in registers? Does the test program have to do anything useful? For example bra -2 is a short program that fits into one register.
    – JeremyP
    Sep 9, 2023 at 12:58
  • bra is not a PDP-11 instruction. br ?
    – dave
    Sep 9, 2023 at 14:08
  • What do you want for an online reference? On the 11/05 and 11/10 (only), the registers are in the address space for both console and CPU. Therefore you can toggle in instructions and presumably execute them (as long as PC logic knows to increment by 1 for these addresses). I have never seen any claim that this was useful; you've got at most 7 registers available, including any you need as registers. So I wouldn't expect the capability to be well-documented.
    – dave
    Sep 9, 2023 at 14:20
  • 1
    Don't know about PDP-11 but it worked on the -10s (which also had more registers).
    – davidbak
    Sep 9, 2023 at 20:57
  • 5
    "and it would be nutty to ..." - as if that's ever stopped anyone ...
    – davidbak
    Sep 9, 2023 at 21:19

1 Answer 1


In the PDP-11/05,11/10 computer manual (DEC-11-H05AA-B-D, section 10.5, page 10-3) DEC describes how the PDP-11/05 can execute short programs out of scratch pad memory (SPM or simply SP). Scratch pad memory is DEC's term for a small section of static RAM used to store the PDP-11 registers and other internal processor state.

The manual goes on to give a two instruction program that can be used to validate the basic operation of the processor:

Address            Instruction    Octal

177700(R0)       NOP                000240
177701(R1)       BR.-1*             000777

As noted in the text, the code is specially constructed to accommodate the unique behavior of the PC register when executing out of scratch pad memory:

When executing a program from the SP, the PC (R7) is incremented by one; however, BR instructions always modify the PC by multiples of two. Consequently, a BR instruction must be carefully used in a [SP] program to prevent the PC from being modified to an incorrect address.

In addition to validating the operation of the CPU, executing programs out of SPM can be quite useful for diagnosing memory issues, as it avoids the need to fetch instructions from potentially faulty memory. On my own PDP-11/05, I use the following programs (written by me but possibly invented by others as well), to repeatedly read or write a single memory location:

Continuously read a memory location
(Start execution at 177702)

177700 (R0) XXXXXX  # Address of memory location to read
177701 (R1)         # Scratch location
177702 (R2) 011001  # mov (R0),R1
177703 (R3) 000777  # BR .-1

Continuously write a memory location
(Start execution at 177702)

177700 (R0) XXXXXX  # Address of memory location to write
177701 (R1) YYYYYY  # Value to be written
177702 (R2) 010110  # mov R1,(R0)
177703 (R3) 000777  # BR .-1


Following up with a bit of related information: According to the PDP-11 UNIBUS Processor Handbook (link, Appendix A, page A-14), the PDP-11/05, 11/10 is the only PDP-11 model that can execute a program out of its general purpose registers.

  • 1
    Good reference, thanks. I went looking for such, but failed to find it.
    – dave
    Sep 10, 2023 at 17:47
  • Presumably your BR -1 should be BR .-1 ?
    – dave
    Sep 10, 2023 at 17:48
  • @another-dave: Indeed! I guess that was just my form of pidgin PDP-11 assembly. :)
    – Jay Logue
    Sep 10, 2023 at 18:30
  • 2
    This is the answer. Also found a reference in the KD-11B Processor Maintenance Manual (DEC-11-HKD88-A-D), Page 5-3 which is available for download from bitsavers.org at bitsavers.org/www.computer.museum.uq.edu.au/pdf/… This included the address range for the SPM which was larger than just the processor register space (R0 - R7). A warning that some addresses in the SPM should not be used as they were required for execution of the microprogram.
    – PDP11
    Sep 11, 2023 at 2:07
  • Re the latest edit... I never knew the PDP-11/05 was the only processor that could execute from the General Purpose Registers. I had only ever used this facility when there was a core memory problem. Then it was not possible to execute programs. Later generation systems such as the PDP-11/04, PDP-11/34A, etc., used the more reliable semiconductors so I never needed to execute code in the GPRs.
    – PDP11
    Oct 16, 2023 at 18:16

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .