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I'm trying to understand the interrupt latency on the PDP-11/23 (more specifically the KDF11-A). Diagnostic JKDBD0 test 375 (Test that a TTY interrupt causes an overflow trap) contains the following instruction sequence:

MOV #100, TTCSR ; SET INTERRUPT ENABLE
CLR STATUS      ; ALLOW INTERRUPT TO OCCUR
MOV #1127,-(R2) ; MOVE TO MAILBOX # *******  1127  *******

This implies that the interrupt routine is executed before the MOV #1127,-(R2) instruction, as otherwise a sequence error in the next test arises.

Now test 403 (Test the 'WAIT' instruction) contains the following instruction sequence:

BIS #100,TPS    ; SET THE INTERRUPT ENABLE
CLR STATUS      ; CLEAR THE PSW
WAIT            ; WAIT FOR THE INTERRUPT

This sequence implies that (at least) two instructions are executed before the stack overflow trap as a result of the interrupt is executed.

How can these seemingly contracdictory results be explained?

A few differences in these tests strike me:

  1. In test 375 interrupts are locked out until the CLR STATUS instruction, while in test 403 interrupts are already enabled at the CLR STATUS instruction.

  2. The MOV and BIS instructions have a slightly different timing. According to the KDF11-AA User's Guide the MOV and CLR instructions together take 10,48 microseconds, the BIS and CLR instructions together take 11,31 microseconds, while the interrupt latency is 10,79 microseconds.

  3. In test 375 a trap occurs while in test 403 the interrupt routine is executed.

Does any of these differences play a role in the different interrupt latencies?

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  • What is TPS in test 403? But I think this is nothing to do with instruction execution times. As far as I recall, interrupts occur between instructions, other conditions (enabled, appropriate priority) permitting.
    – dave
    Nov 7, 2023 at 12:59
  • Both TTCSR and TPS are the DLV11-J channel 3 Transmitter control/status register. Setting the interrupt enable generates an interrupt when the transmitter is ready to accept a character.
    – JosF
    Nov 7, 2023 at 15:20
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    Is there any difference between the state of the transmitter? It seems to me that, as long as the current processor priority permits it, that you get the interrupt as soon as (1) the transmitter is ready, (2) transmitter interrupts are enabled, (3) there is other DLV interrupt pending (channel 3 tx has lowest internal prio). So in test 403, is there some reason why the interrupt is not immediate?.
    – dave
    Nov 7, 2023 at 19:31
  • Also,in test 375, why should a tx-ready interrupt cause an overflow trap? I take it from what you say for test 403 this is a stack overflow trap. But why? Is the K-stack not set up to handle the interrupt?
    – dave
    Nov 7, 2023 at 19:37
  • Your remarks on the state of the transmitter probably answers the question. In test 403 the transmitter buffer is loaded with a CR and immediately thereafter the interrupts are enabled. This means that the interrupt will occur when the channel is ready to accept another character, after the CR has been sent to the console. That will take enough time to get to the WAIT instruction. Thanks!
    – JosF
    Nov 8, 2023 at 7:54

1 Answer 1

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another-dave pointed me in the right direction. In both tests the DLV11-J is used as an interrupt generator. In test 375 the DLV11-J channel is ready to accept a character and enabling the interrupts therefore immediately generates an interrupt. In test 403 the transmitter buffer is loaded with a CR and then interrupts are enabled. This means that the interrupt will not occur immediately but only when when the channel is ready to accept another character, i.e. after the CR has been sent to the console. That will take enough time for the processor to get to the WAIT instruction.

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