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PDP-8 heavily relied on conditional skips: instructions that under some circumstances would skip the following instruction. Among them are, for example:

  • ISZ
  • SZA/SNA/etc. group of instructions
  • many IO instructions

While it is perfectly clear what should happen when the following instruction is also 1-word, there are still some EAE 2-word instructions , that have either immediate value or direct 12-bit address in the second word.

My question is thus simple -- would conditional skip instructions skip both words of the following 2-word instruction, or just first, thus leaving second word as an unexpected (or probably incorrect) instruction?

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    To my understanding the basic skip instructions always incremented PC by 1 if true. Thus a usage with (later add-on like) EAE double wort instruction isn't a great idea.
    – Raffzahn
    Jan 12 at 12:27
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    @Raffzahn You're right; the obvious thing is what happens! There is an explanation below Jan 12 at 13:59
  • Intra-instruction skips are a common hack on old architectures where everyone used assembler a lot. Judicious use of a 2-word instruction, and skipping into that instruction's 2nd word, has uses. I've seen this used pretty much on every CPU where assembly hacking was a thing. Even without a skip instruction. Jumping into an instruction could save code space. Say on Z80 a common trick for skipping a 2-byte instruction is prefixing it with 0x21 (LD HL, #word). Jump to the 2-byte instruction will execute it. Falling through the LD HL will skip it. Jan 12 at 21:30
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    @Kubahasn'tforgottenMonica the question is not about some programming tricks of misaligned jumps/branches, but instruction skips. Those do not carry any distance information. Complete different case as with later microprocessors.
    – Raffzahn
    Jan 15 at 11:40
  • @Kubahasn'tforgottenMonica Here is a question about exactly that on the Z80 May 10 at 7:46

1 Answer 1

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The various PDP-8s have a few subtle differences, which could potentially include whether you can skip double-word instructions like your question implies, but I doubt that. There is no mention of such a thing on this page discussing the different options and their incompatibilities, so it's a safe bet that all PDP-8s had the same semantics as the PDP-8/E, /M and /F which I describe below. And SKIP instructions do generally only exist on fixed-length instruction machines, like the PDP-8 (mostly) was.

This answer is written from information sourced from PDP-8/E & PDP-8/M & PDP-8/F Maintenance Volume 1 (PDF warning).

Here is a description of the datapath allowing the program counter to be incremented on the PDP-8/E, this is figure 3-2 in the book):

  • There is a flip-flop called SKIP, and a signal called SKIP L which applies the SKIP flip-flop to carry-in logic.
  • Signals EN0, EN1 and EN2 places the contents of the Major Registers into ADDERS. The major registers include CPMA and PC (relevant to your question), and the obvious Accumulator, MQ, Memory Buffer, etc. etc.
  • The result of ADDERS is fed into a shifter implementing the miscellaneous rotate operations. Obviously this part does not rotate anything when dealing with the Program Counter. The result of this shift goes to MAJOR REGISTERS BUS, to be loaded into CPMA which is the register for holding addresses, and is part of the interface to core memory.

This all would imply that the PC may be incremented by either one or two with each fetch, and the way this happens is by loading PC into CPMA, and from MA back to the PC, both of which go through ADDERS.

You can find this information on page 3-22 of the maintenance volume as well. To see how this datapath is used to increment the PC by 1 or 2 during an instruction, here follows a description of figure 3-8 which is the FETCH state flow diagram.

  • TS1:

    • Clear the SKIP flip-flop
    • Read the instruction (this has the side-effect that the new value of PC is now on the MA bus)
    • Load MA + 1 into the PC; (the PC points now to the next instruction)
  • TS2:

    • (some values get moved around in preparation for the execution of the instruction, I'm suppressing this detail for clarity)
  • TS3:

    • (The instruction gets executed, again I'm suppressing a lot of detail here) SKIP might get set at this point
    • Instructions which reference memory set the CPMA register to the correct address. The JMP and JMS instructions assert PC LOAD here so that MA is loaded to the Program Counter (See 3.37.3)
  • TS4:

    • Depending on if the executed instruction uses CPMA for its own address calculation, and if an interrupt happened, Either
      • No interrupt or SKIP happened, then PC + 0 gets loaded to CPMA.
      • No interrupt happened, but a SKIP happened, then PC + 1 gets loaded to CPMA.
      • An interrupt happened! CPMA is cleared, and a JMS is loaded into the Instruction Register (nifty, isn't it?)

This all means that:

  1. before an instruction is fetched, the program counter is incremented by one
  2. during an instruction, the program counter is optionally incremented by one, which is what SKIP L does
  3. during or after an instruction, the program counter may be loaded from MA, which is how JMP, JMS and interrupts are implemented

So the answer to your question is no, the PDP-8 does not skip both words of a double-word instruction).

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