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While researching this answer about incrementing the program counter, I found something I thought was a little odd in the FETCH state flow diagram, which is figure 3-8 of the PDP-8/E & PDP-8/M & PDP-8/F Maintenance Volume 1 (PDF warning).

That diagram seems to imply that an interrupt is only serviced after certain instructions, such as those not needing to use the CPMA register. That does not include AND, TAD, ISZ, DCA, JMS, the first 5 instructions. (The CPMA register is one for calculating addresses; it can load data from the program counter and the instruction register, and can react to certain bits in the instruction register).

But that would mean that an interrupt will not be serviced after any of these five instructions! That could mean that a programmer would need to take care to schedule any of JMS, IOT, OPR to make the interrupt latency acceptable. Or, a malicious code-sequence, for example a subroutine that jumps to itself, could effectively disable interrupts.

I think I would have known about something like that. Am I misunderstanding something?

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    The possibility of faulty or malicious code freezing the machine was common in those days, even for machines much more complicated than the PDP-8. Except for the rare specialized machines designed specifically for time sharing, nobody worried about needing occasional operator intervention to get the machine back on track.
    – John Doty
    Jan 12 at 17:12

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If you look at figure 3-13 in that manual, it shows the same initial steps for FETCH as in figure 3-8, but in parallel it checks the interrupt request line and serves the interrupt, if present.

So I'd assume figure 3-8 is simplified, and leaves out those steps as they are not relevant for this figure.

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