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On the one hand, I get the impression that memory chips around 1980 could be accessed no faster than 2 MHz.

On the other hand, the 68000, introduced in 1979, had a typical clock speed of 8 MHz.

How did the latter work with the former? Admittedly the effective speed was half the rated speed, that is, the 68000 used two clock cycles as its minimum time quantum. Is that half the answer?

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    That explains why the bus cycle of a 68000 takes 4 CPU clock cycles. – JeremyP Jul 21 at 7:44
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If you look at the datasheet of a typical DRAM chip of this era, say the Mostek 4116, it indeed has a cycle time of 375ns, so you can't access it at more than 2.6 MHz.

But don't confuse the clock rate of a microprocessor with the bus timing. Looking at figure 4-1 of the 68000 datasheet, a simple byte read or write bus cycle take 8 CPU cycles, and the simple word read or write bus cycles in figure 5-1 also take 4 cycles, so indeed RAM access time was 1 MHz for a 8 MHz CPU clock.

Note that the whole cycle determines bus access rate: The address must be valid first, then the address strobe AS changes, then data is provided and validity signaled by DTACK or UDS resp.LDS. That you see the data valid for four cycles means nothing by itself.

Also, nearly all microprocessors had a way to delay bus cycles for slower devices on the bus ("wait states"), so even if some CPU happened to be faster than RAM, it could always be slowed down to match RAM speeds.

In fact, clock rate of a microprocessor doesn't say much about how "fast" it is if you compare different models. For example, the Z80 typically had a higher clock than a 6502, but also needed more cycles to complete an instruction.

So, always look at the details, don't rely on raw numbers.

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    On a 68k, it's /DTACK that could make the CPU wait for slower memory and I/O - as long as /DTACK is high, the CPU wouldn't pick data from the bus and complete the fetch. (That's why a quite famous 68k tinkerer's journal of the 80ies was called DTACK Grounded - meaning "68k running at full throttle") – tofro May 13 '17 at 22:05
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    I see what you're saying, but are you sure S0-S7 refers to clock cycles? As far as I remember, the simplest instructions like register-register add, took a total of four clock cycles (two read, two execute), so RAM access time was at least 2 MHz. I could have sworn instructions to read or write larger quantities, did a word every two cycles once they got going, but I might be misremembering. – rwallace May 13 '17 at 22:05
  • Okay, it looks like I was misremembering, looking at the datasheet, it seems to be saying each word takes four clock cycles, so that is consistent with the memory access speed really being 2 MHz. – rwallace May 14 '17 at 3:36
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    There are 8 states in a bus cycle, but there two states for every clock cycle. In S0 the clock is up, and in S1 the clock is down. So there's actually 4 clock cycles in a bus cycle. In section 5.8 of the datasheet you link it reads "The standard M68000 bus cycle consists of four clock periods (eight bus cycle states) ...". – Ross Ridge May 14 '17 at 9:09
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    Section 4, by the way is talking about bus operation when operating in "8 bit mode", which was normally used only with the 68008 (where it was the only mode). – JeremyP May 15 '17 at 10:18
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The 4 clock cycles per memory access was for instruction fetch and the 68000 could actually take longer. (Internal Architecture of 68000 was 3 16-bit Arithmetic Logic Units; 2 for Data registers and 1 for Address meaning that 32-bit addresses took longer to calculate. This was from IBM XT/370 info that used a 68000 microprogrammed to execute IBM mainframe code.) Note that later computers loaded their O/S code into RAM. The 68000 era computers used MOS Program ROM which was quite a bit slower so wait cycles had to be added.

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