I'm poking at the Intel 8086/8088 (iAPX 86/88) User's Manual, which states on page 2-29 (PDF page 48), table 2-4, CPU State Following RESET, that the state of the CPU after the RESET pin rising followed by going low is guaranteed to be:
- Flags = Clear
- Instruction Pointer = 0000H
- CS Register = FFFFH
- DS Register = 0000H
- SS Register = 0000H
- ES Register = 0000H
- Queue = Empty
Curiosly, this means that CS:IP points at physical address FFFF0H (1 MiB minus 16 bytes), and that the stack begins somewhere in the lowest 64 KiB of memory because SS (the stack segment register) is cleared, but SP (the stack pointer register) is not guaranteed to have any particular value. If SP happens to take on the value FFFFH on reset, then SS:SP becomes physical address 0FFFFH = 65,535, resulting in a possible range of physical address 00000H through 0FFFFH pointed to by SS:SP; thus 64 KiB.
Consequently, one of the first few things any CPU bootstrapping code would seem to have to do is to actually initialize SS:SP to some sensible value, probably immediately after the intersegment jump instruction recommended (page 2-29, PDF page 48) to be available at physical address FFFF0H. Only after SS:SP is explicitly initialized is it even remotely safe to perform any operations that use the stack.
This would be exacerbated by Intel specifically reserving the lower 128 bytes of the address space (0H through 7FH, page 2-16 figure 2-21, PDF page 35; also in text on page 2-15), so whatever code runs immediately on CPU reset must specifically make sure to not clobber that memory area.
Is my reading of the manual correct and Intel guarantees nothing about where SS:SP will point after RESET on the 8086 or 8088 other than that SS is 0000H, or am I missing something that is relevant here?