I most online documentation, I find the addressing mode for BRK to be "implied", which is logical. In the W65C02S datasheet however, it is set as "stack":

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Is there some reasoning behind this, or is this an error in the docs?

2 Answers 2


CPU datasheets like these are intended for hardware designers and show things from their point of view. The CPU performs stack operations when executing these instructions, so that's what got documented.

You will note that the other instructions marked "s" are RTI, RTS, PLx, PHx, etc, which are also one-byte instructions which manipulate the stack, and so it's consistent to put BRK in this addressing mode group. This does not change in the later 65816 documentation, which additionally lists the new COP instruction (basically another BRK but using a different vector) as "s".

Where this scheme goes to pot is JSR: it's marked "a" to say it takes an absolute address, which it does, however it also operates on the stack. In this case, the document author chose "a" over "s".

So BRK is "s" merely because somebody arbitrarily decided that single-byte opcodes which touch the stack are "s" rather than "i". WDC's documentation is famously a bit vague and misleading in places, and this is one such example.

  • 1
    I guess, it's really a matter of how many categories/modes you want to have in your datasheet. Technically, the address mode should be "indirect, implied" (BRK takes an indirect target, from an implied address), but that's a mode/category with just a single, lone member. So you're looking at what else you already have that may apply somehow in some way… (The side effect here is that the categorization now highlights the write operation to the stack and not the read for to the vector.)
    – masswerk
    Commented Apr 16 at 4:41
  • PS: Arguably, the stack mode is kind of a misnomer, since the main purpose of BRK is not that of yet another push method, but a change in control flow, which necessarily emphasizes the read operation for the target. But, see above.
    – masswerk
    Commented Apr 16 at 4:59

Chi esce dalla gallina gratta come una gallina

(The Chick of a Hen Behaves Like a Hen - Italian Proverb)

BRK is a software interrupt and interrupts have by definition stack assigned as addressing type, as noted in section 4 Addressing Modes of the 2016 data sheet:

4.10 Stack s The Stack may use memory from 0100 to 01FF and the effective address of the Stack address mode will always be within this range. Stack addressing refers to all instructions that push or pull data from the stack, such as Push, Pull, Jump to Subroutine, Return from Subroutine, Interrupts and Return from Interrupt.

(emhasis mine)

More Than Meets the Eye

Opcode lists for CPU's like the 6500 or similar look simple at first An opcode and a single operand, which usually is defined by an addressing. Opcode tables compress this even more to a single marker.

The only issue is that this view is already oversimplified before any table is created. Even 'simple' one-address machines, like the 6502, do in fact almost always operate on multiple operands. Simply because unary operations are only a few, the majority are binary.

A basic ADD #5 encodes two operands to be added: The value 5 and whatever the A-Register holds at the time (*1). It's easy to forget about the implied A, as the 6502 doesn't allow much variation for ALU operations. Load/Store in contrast do support multiple register operands: A,X and Y. Just because the way the mnemonic 'implies' that register doesn't change that it's a binary operation (*2).

Pick Your Poison

While one can easy ignore the binary operand issue for 'simple' cases, some operations are more complex. To make this go with the 'one operation one addressing mode' principle - and make it fit into a single marker in each table cell, one has to choose one. Best to take the most user visible, keeping the projection of single operand single addressing mode up.

  • No big deal in case of arithmetic operations and the A-register.
  • Similar a subroutine return (RTS), implying stack usage, but
  • a subroutine jump (JSR) already leaves the cosy terrain by having two implied addressing:
    • an absolute target address plus
    • an implied stack address to store the PC.

Still, with JSR the decision weather to put 'a' (for absolute) or 's' for stack is simple: The user writes absolute address, so 'a' for absolute it is.

BRK in turn isn't a easy, as all of its operations are implied:

  • Storing PC and Status (P) onto stack,
  • decrementing the S-register and
  • fetching its interrupt vector from $FFFE/F

Weighting these the stack operations seems the more relevant as it changes memory content (and the S-Register).

Ober Sticht Unter

(Roughly: King Overrules Jack)

Importance is the general theme here:

With just one spot to mark a single addressing mode the most relevant has to be selected to a list akin to:

  1. Source visible - An addressing mode visible in mnemonic / operand field
  2. Memory write access
  3. Memory read access

*1 - When being pedantic one could note it's 3 as there must be the target as well. But being a 2 address machine the target is always the first ... tat is unless it's a store. Yeah, as more as one thinks about those mnemonics as weirder it gets.

*2 - MOS followed the same simple structure as Motorola and Intel did with 6800 and 8080 of 'encoding' one register operand into the instruction mnemonic. A move that simplifies first assembler as lot by bloating the number of mnemonics (*3). Much of the clarity of the Z80 Assembler was gained by enrolling 7 different 8080 mnemonics into a simple LD (not to mention that the 8080 already reduced 59 8008 mnemonics for the same purpose into those 7). An step made possible by development of more complex assemblers. A step the MOS never took - and Motorola only with the 68k. Otherwise 6502 Assembly could look as symmetric like

  • LDA -> MOV A,<target>
  • LDY -> MOV Y,<target>
  • STA -> MOV <target>,A
  • TAX -> MOV X,A
  • CPY -> CMP Y,<target>
  • INX -> INC Y
  • INX -> MOV A,*
  • LDY -> MOV A,*

And so on, turning 21 mnemonics into just 4 (or 29 into 5 when including the branches).

*3 - Even better for marketing, as they could shout about how many instructions a CPU had. More is better :))

  • 4
    The 6502 has such an irregular set of allowed and disallowed combinations of operands, trying to normalize the assembly format might make code more readiable, but at the expense of making it harder to judge when code could be reworked to be more efficient. Given four registers A, X, Y, and S, someone asked to guess which combinations of registers were supported by transfer instructions probably wouldn't guess the six choices the 6502 actually supports.
    – supercat
    Commented Mar 9 at 21:46
  • 3
    Not sure why a literal-ish translation for "higher beats lower" would involve playing cards (unless they're not playing cards but a literal king and knave in a monarchy). And I'm certainly not going to tell a native German speaker what German phrases mean :-) But, as with most of your answers, the detail is impressive.
    – paxdiablo
    Commented Mar 9 at 23:59
  • 5
    @paxdiablo It's a saying based on Schaffkoppen, a card game played with German card featuring Ober and Unter (Roughly Officer and Non-commissioned Officer - the cards show an army) instead of Queen and Jack. Ober trumps highest in the game. The cited term is a part of Schaffkopp language that moved into common use, essentially meaning someone higher ranking (as in more experienced) did already settle the issue, no need to oppose anymore.
    – Raffzahn
    Commented Mar 10 at 0:39
  • 1
    I'd say, the main purpose of BRK is not that of a push operation, though. It's really about a change in control flow, which is also what should be emphasized by the address mode, as in "indirect, implied", which really doesn't exist in the datasheet. (Therefore, "What else do we have…?")
    – masswerk
    Commented Apr 16 at 5:09

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