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The initial memory board shipped with the Altair 8800 was a 1K board using one to four pairs of Intel 8101 1024 bit (256 × 4) static RAM. Altair then started working on a 4K dynamic memory board. The initial version, the 88-4KD, was apparently quite problematic; it's not clear to me whether it included refresh circuitry. That board never worked properly, and so a complete redesign was done, producing the 88-S4K 4k Dynamic RAM board. That apparently did not include entirely independent refresh circuitry (allowing it to be used in the same way as a static RAM board); from the page linked above:

The Altair board obtained its essential dynamic RAM refresh pulse from the 8080 microprocessor chip by a process called "cycle stealing."
...
They called the board a Synchronous RAM board meaning it relied on the CPU for refresh timing signals -- "no single shots" the brochure quoted. The latter presumably referring to their earlier problematic dynamic RAM board.

How did the DRAM refresh work on the first and second Altair RAM boards? Please include references wherever possible.

Useful references for your answer may include the 4K Dynamic RAM board schematic, though it's difficult to read as it lacks part numbers. A letter from MITS seems to indicate that they were looking at Signetics 2604 devices as they were having trouble sourcing 2017 DRAMs, but the pinouts on the schematic appear to match that of the NTE 2107 4K Dynamic RAM.

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Your link gives "MITS - 88-S4K" as name of this particular DRAM board. Googling finds documentation for this board here, and on page 2-5 under "Refresh Ciruits" it states

The 12-stage counter provides the refresh address, and the counter frequency is supplied by the Phi2 clock. Flip-flops A detect when it is time to refresh. Refresh occurs near the end of SM1 (Machine Cycle One) if the computer is running.

with figure 2-1 on the following page illustrating the mechanism. Pages 2-10 ff. contain more details about the refresh operation.

So it did include "independent refresh circuitry", and it looks like it was designed as a drop-in replacement of the static board, as it says "there are no wait states", and it works both when the CPU is stopped and when it is running. However, the clock signals were not independent.

As for "how does the board refresh without stomping on CPU memory accesses?", the short explanation is that it does refresh in the T4 state of machine cycle 1 (M1), which is used internally by the 8080 CPU to decode the instruction, and therefore doesn't do a memory access.

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  • Great find on that documentation! But if there are no wait states, how does it ensure that it's never refreshing DRAM while the CPU is trying to access it?
    – cjs
    Mar 11 at 10:26
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(Note: this answer is based on information from dirkt's answer, and especially the excellent documentation he dug up.)

I don't have information about the earlier (unreliable) board, the 88-4KD. However, I can summarise the 88-S4K refresh operation. This is based on the "Theory of Operation" section of the 88-S4K manual (see further references below). Note that this explanation elides many of the details in the manual itself in the interest of brevity and comprehensibility.

The 88-S4K board provides "hidden" refresh; that is, it is invisible to the CPU and does not slow or block the CPU in any way.

The board has a counter that is incremented with every other cycle of the 2 MHz system clock (i.e., every other T-cycle). This counter serves two purposes: it supplies the address of the next refresh (a 6-bit DRAM row number ranging from 0 to 63, incremented with every refresh) and every 32 counts it generates a refresh set-up signal. This refreshes a row every 32 μs or so, refreshing all rows within a period of 2.048 ms, almost exactly at the 2 ms specification of standard DRAM.

When the refresh circuitry is triggered by the counter, it then waits for the next S-100 bus SM1 signal (generated by the 8212 System Controller on the CPU board) that indicates the start of an instruction fetch machine cycle (M-cycle), also called an M1 cycle. All instruction fetch M-cycles consist of four T-cycles; during the first three of these (T1, T2 and T3) the instruction is fetched from memory. During the fourth cycle (T4) the CPU decodes the instruction and does not access memory.

The refresh circuitry uses a pair of flip-flops to count the T-cycles during an M1 cycle and after T3 has completed a DRAM refresh is initiated. The refresh has two parts:

  1. The buffer for for address lines A0-A5 from the S-100 bus is disabled and the buffer that allows the counter's refresh address bits to drive the board's A0-A5 lines is enabled. This supplies the refresh row address to the DRAMs. (The DRAM A6-A11 address lines may be indeterminate during refresh.)

  2. The RCE signal is asserted; this drives the CE pin of the DRAMs to enable them. The DRAMs' /CS chip select signal is not asserted; that's not necessary for a refresh and negating it ensures that the chips will neither read their inputs nor drive their outputs.

On completion of T4, the refresh circuitry is deactivated and the DRAM board resumes normal operation until the next refresh set-up request is generated.

The above describes how the refresh circuit works during the RUN mode of the Altair 8800 when the CPU is not halted. In the 8800 STOP mode (selected from the front panel) the CPU is in the M1-T2 state (except when depositing to or examining memory) and the above technique will not work. The STOP mode is detected by the S-100 RUN signal being low; in this case some additional circuitry allows any current front panel examine or deposit operation to complete and then the refresh proceeds immediately as above. The operation is similar when the CPU is in a halt state.

It should be noted that because the refresh must occur in a single T-cycle this board requires fairly fast memory. The standard memory provided is TMS 4060-2 (200 ns access time; 450 ns read cycle time) or similar, one of the faster parts available in 1976. This is sufficient for a 2 MHz system clock (500 ns per T-cycle) but will almost certainly not work with a faster (e.g., 3.5 MHz or 4 MHz) CPU.

References

The following documents provide useful additional information, espcially if you're digging into the explanation in the 88-S4K manual itself.
  • 88-S4K manual
  • Details of Z80 memory access cycles
  • TMS 4060 DRAM datasheet

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  • Interestingly at the time Mostek was already doing DRAM, but it might not have been common yet.
    – Yuhong Bao
    Mar 12 at 5:36

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