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How does an original 6502 behave if the ready pin is being held during a reset/power-on event?

  • Would it pause CPU start-up entirely, delaying when some or all of the 6 internal cycles are executed? (the ones where it goes through the motions of preparing for an interrupt, except that the stack operations are hacked to be reads instead of writes)

  • Or would get past that and pause/loop the reading of the first byte of the reset vector?

  • Or would it only take effect once the CPU begins reading the first real opcode, looping the reading of that byte?

I'm particularly interested in how this situation would affect the data bus and address bus.

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  • IIRC it will simply wait and repeat the first cycle.
    – Raffzahn
    Apr 3 at 23:07

1 Answer 1

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From the "MCS6500 Microcomputer Family Hardware Manual (January 1976)" (p. 37)

The RDY input delays execution of any cycle during which the RDY line is pulled low. This line should change during the Phase One clock pulse. This change is then recognized during the next Phase Two pulse to enable or disable the execution of the current internal machine cycle. This execution normally occurs during the next Phase One clock; timing is shown in Figure 1.13.

The primary purpose of the RDY line is to delay execution of a program fetch cycle until data is available from memory. This has direct application in prototype systems employing light-erasable PROMs or EAROMs. Both of these devices have relatively slow access times and require implementation of the RDY function if the processor is to operate at full speed. Without the RDY function a reduction in the frequency of the system clock would be necessary.

The RDY function will not stop the processor in a cycle in which a WRITE operation is being performed. If the RDY line goes from high to low during a WRITE cycle the processor will execute that cycle and will then stop in the next READ cycle (R/W = 1).

I'd say, given that figure 1.13 (see below) shows R/W immediately going high at the start of the reset sequence and remaining high during the entire sequence (indicating a read cycle), this should apply to any cycle of the reset sequence. Since the expressed purpose of RDY = 0 is to inhibit any fetch cycles, this should mean that when RDY goes low, the current cycle is delayed (i.e., the progression of the clock to Phase 2 inhibited) and there should be no noticeable bus activity. Compare figure 1.13 below, showing no bus activity before Phase 2 goes low for the fetch of the reset vector. However, mind SYNC (6502 specific) going high during the 3rd cycle of the sequence. (I have no idea what the implications of RDY = 0 for this SYNC spike might be.)

(Notably, this is just my interpretation of the manual and not based on empirical data.)

MCS650x timing: start-up sequence

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  • I that sync cycle should only apere if RDY is already release. If pulled (again) during that cycle it would extend as long as pulled - see the right side of that graph.
    – Raffzahn
    Apr 4 at 2:32
  • @Raffzahn You're probably right, I also think SYNC should stay high when RDY goes low in this phase. But I wasn't sure about this and thought it may be something to be aware of…
    – masswerk
    Apr 4 at 2:45
  • Does anyone know experimentally whether the reset would keep reading the same address in the $01xx range while READY was low, or decrement each cycle? The logic which handles SP updating on "push" operations would normally never have reason to care about the state of RDY, and there would generally be no downside to having SP get decremented on each cycle even if RDY is held low.
    – supercat
    Apr 8 at 22:15
  • @supercat I think, the only variable here is that the NMI line is low (active). Notably, the interrupt sequence is asynchronous. However, I suppose, the cycle should be still halted before the fetch. But, again, no experimental data. (Generally, this is a processor built to low cost, as opposed to what may be nice to have. So there shouldn't be much extra going on, in terms of special case. There's just "is it read or not", to cope with slow memory.)
    – masswerk
    Apr 9 at 18:57
  • % And, as stated in the manual, if it's not a write cycle, it's a read cycle (there are just these two states), so – in theory – the delay should apply. (Again, as for any statement in any manual, evidential data may diverge.) Also, as we fetch the vector, NMI is already high.
    – masswerk
    Apr 9 at 19:05

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