I wonder if there were 3D accelerators (that is, a device that calculates rotations, scaling, texturing, etc. for 3D points) built on discrete logic (7400 series, most likely its fastest variants, such as 74F) without the use of ASIC or co-processors (for example, an 8087 type mathematical coprocessor). And I don't mean with shaders.

If so, what characteristics did they have (how many triangles per second, etc.).

If not, what was their hypothetical speed (triangles per second)?

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    The Wikipedia article on the E&S LDS-1 includes a link to original documentation. A quick perusal shows multiple references to 7400-series TTL, but it is not immediately clear whether any ASIC-like components were used. If the LDS-1 does not fit your desired definition of 3D accelerator you might want to revise the question.
    – njuffa
    Commented Jun 22 at 0:34
  • Unless calculators count, discrete TTL for trigonometric functions? Pre-8087? No. Univac mainframes didn't have that, and I'm sure nobody else did. What did NASA use? Commented Jun 22 at 2:48
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    @Jess Fuckett Volder's 1959 publication on CORDIC predates the existence of 7400 series TTL. CORDIC was actually the name of a computer (that used the algorithm we now refer to as CORDIC): "The COordinate Rotation Dlgital Computer (CORDIC) is a special-purpose digital computer for real-time airborne computation. [...] CORDIC is an entire-transfer computer; it contains a special serial arithmetic unit consisting of three shift registers, three adder-subtractors, and special interconnections." FWIW, the 8087 used the CORDIC algorithm in conjunction with rational approximations.
    – njuffa
    Commented Jun 22 at 3:21
  • I'm sorry; I assumed the question referred to commercial hardware. NORAD SAGE probably had it, too Commented Jun 22 at 3:41
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    If you extend that to 'accelerators' in general, in 1979(ish) I was working in MRI. The 32 bit Perkin Elmer machine we had (TTL/ECL built) (with a 160 MB hard drive, divided into 16 10 MB 'systems'!!!) had a 'Deanza' FFT accelerator (19" rack mount, 2U high), which appeared to be stuffed full of discrete logic, whether ECL or F was not clear.
    – Neil_UK
    Commented Jun 24 at 5:26

4 Answers 4


Since you list texturing in the hard requirements for a 3D accelerator, the earliest instance of a 3D accelerator could have happened only 1974 or later – the idea of algorithmic texture mapping comes more or less completely from Edwin Catmull's seminal 1974 PhD thesis.

That's three years after the intel 4004; someone who would build an accelerator for a domain-specific task (3D texturing) would start by identifying at which task the contemporary integrated CPUs or still prevalent distributed high-performance computers of the time were the slowest, i.e., what needed acceeleration the most. There's two things you'll notice when you do 3D anything:

  1. you need memory bandwidth,
  2. you need multiplications, a whole lot of them

Memory bandwidth basically already says that "7400 series" won't cut it. You want modern memory ICs. That aside, multipliers are huge. Here's a quick optimized mapping of a naive 8×8 bit combinatorial multiplier to CMOS logic:

That thing has 1122 wires (not counting power supply/ground), and consists of 16 D-Flipflops, 338 NANDs, 292 NORs and 127 NOTs. The longest combinatorial path is 37 gates deep. Even if you can somehow squeeze the two-input gates into quad-packages and the inverters into hexa-component packages, you end up with roughly 200 ICs.

Sure, that thing, built from 74Fxx, would then be able to run at ca 1/(37 · 3.4 ns) / 2 = 3.97 MHz at best, and assuming half the gates toggle per operation, would use upwards of 16 W. (realistically, it would use more power, this design necessarily being large and hence the bus load, too, and would be much slower. But, this is the ballpark.) This is a single 8×8 bit multiplier, so, scale that up by 4 and you got something like a single reasonably flexible multiplier unit that you can use in troves to build accelerators. And this is just one part of it – you need address generation, texture memory interfacing, output memory interfacing, control interfacing…

I mean, nearly 4 million multiplications per second, that's nice. Given, say, 3 years from PhD thesis to commercial demand for a 3D product, the Z80 running at 4 MHz was priced 59 $/core. Since 3D work tends to be pretty parallel in nature, a reasonable accelerator architecture could have just designed Z80 boards, put them in parallel and have them churn out multiplications in software at maybe 200 kMul/s, and still would have come out ahead in MIPS/W and MIPS/$.

So, nope, doesn't sound to me like you would have ever wanted to build a 3D accelerator – according to your definition of it – in discrete hardware.

There's been discrete-built accelerators for 3D calculations – trajectory paths of rockets going to the moons or the other side of the iron curtain etc – but not in the sense you mean "3D accelerator". These were very special purpose, with every arithmetic operation being thought about in terms of how many bits are needed, and not much memory interfacing at all. I can imagine there's been separate multiplier ICs – but these would be too highly integrated circuitry to count as "discrete gates" in what seems to be the spirit of your question.

  • What program did you make that graph with?
    – Meatwad
    Commented Jun 22 at 18:58
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    The graphical embedding (i.e., the picture you can look at), with dot, the graphviz default layouter for directed graphs (i.e., unlocated sets of arrows and vertices). The directed graph itself is the output of using yosys on the verilog in the gist I linked to, mapped to the cmos_cells.v/.lib that come with the examples directory in yosys' source code. (I've also got a mapping library for classical gates available as 74AC×, instead of just NOR/NAND/NOT, but it's not good enough for the public.) Commented Jun 22 at 19:02
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    Of course, no one would have built such a thing, because by 1976 or so, companies like TRW were already producing general-purpose 12- and 16-bit multiplier chips. In fact, my senior project in college (1979-80) was to design a DSP coprocessor for the PDP-11 around such a chip.
    – Dave Tweed
    Commented Jun 23 at 15:43
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    nice, @DaveTweed! (and frankly, cool senior project!) Yeah, basically the age of discrete gate computing was gone when 3D "became a thing", even for people that made computer graphics commercially. It would seem to be causally linked to me: can't really feasibly think about 3D computer graphics if your memory bandwidth is limited by the fact that you're plugging together logic gates on PCBs with traces of copper. Commented Jun 23 at 15:48
  • I think using a multiplier chip or bitslices would probably count as discrete logic here since it's not an ASIC, FPGA, or based on a microprocessor.
    – davolfman
    Commented Jun 27 at 21:40

3D accelerators in the sense you are describing for a pipeline rendering triangles etc. only came up after discrete logic was already phased out for much higher integration. So you'd have accelerators using a second 68000 CPU, for example.

Discrete logic CPUs were much earlier, and usually then also implemented some kind of I/O functionality (like in the Xerox Alto), and maybe 2D blitting support, but no 3D pipeline in your sense.

Anything similar to at least a part of the 3D pipeline in your sense (e.g. like what Nvidia did with the NV1) would have been too large for discrete implementation.

If you extend the question and allow "3D accelerators" in a more general sense (any kind of support for 3D calculations, but not necessarily a pipeline rendering triangles), there might be some examples.


This sounds quite hypothetical, more important seems to miss the timeline, as 3D accelerators only became a thing to create when large scale real time 3D display solutions, needing such, became a possibility. At that tim, and as DirkT explains, any designer would have used ASICs or full custom chips. Before that, it was the addition of hardware based floating point used to calculate those.

So pick any discrete build FPU.

Equally, if not more important:

3D accelerators need triangles, but 3D does not need triangles

The widespread reduction of everything down to a single data type of triangles and working on them was was what enabled 3D accelerators to be build. 3D rendering can happen from any object description. in most cases objects can be described with way less data points and handled with less operations if described in more complex objects than triangles.

Just imagine a sphere. It can be described with a single set of coordinates and a diameter. Software can use this optimal compact data set to render that sphere at any imaginable resolution. In addition it will be faster any less resource consuming. Same is true for other objects. Great, isn't it?

Except each of those objects is based on their own rule set, needing a specific implementation plus rules for interaction. That's not a big deal if we talk software. Add one or a few functions and another object (data) type can be used to model the scene. All using the same basic FPU (if at all). Doing the same with hardware is way more challenging than adding a few kilobytes of code.

On the other hand, a hardware for one single simple data type can be build with reasonable effort - and turned into pipelines and parallelization and so on. Of course not all those nice specific data types had to be turned into that simple one. Creating the need for thousands of triangles each with 9 coordinate values instead of a single set of 4 values for a sphere - and a race for ever faster triangle processing to close the gap to what the spherical solution had provided.

  • "ASICs or full custom chips." Not quite sure this is the terms you meant – an Application Specific IC (ASIC) is a fully custom chip for your application. Commented Jun 22 at 16:28
  • @MarcusMüller Not really. For one, with this definition any chip is an ASIC as ale are made for an application specific use. More relevant, the point is that ASIC are usually made on less than fully custom designs - at least back in the days. Usually made as gate-array or, less often, as sea-of-gates. An area nowadays occupied by FPGA.
    – Raffzahn
    Commented Jun 22 at 17:19
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    @MarcusMüller by that definition an 80387 is as well an ASIC, right? Or what is the difference? Ignoring the quite different ways of creating chips makes the whole naming superfluous, doesn't it?
    – Raffzahn
    Commented Jun 22 at 19:36
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    That's a bit of a corner case: it's a companion chip for exactly one purpose; but, it is used for general purposes in a wide range of devices. I think there's things where the distinction is easier and some where it's harder. As an example on the "non-application-specific" end is certainly things like general purpose opamps, voltage regulators, memory ICs. On the other end would be something like a decoder for the channel code used on fiberoptical long-haul interfaces, a power management IC that was designed specifically to supply power for the N power rails of a phone baseband+CPU SoC. Commented Jun 22 at 19:45
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    But yes, if you asked me, the 80387 is an application specific IC, an ASIC. No problem with that definition, whatsoever. Its sole purpose is to enable a single CPU type to deal with floating point. You can't use it to teach floating point to anything else, you can't use it as standalone multiplier IC next to a programmable logic device of its day, and it's not conforming to any standard other than that of its manufacturer. Commented Jun 22 at 19:45

Although not exactly "3d" by modern standards, the arcade machine Star Ship from the 1970s used hardware scaling to allow an enemy ship sprite to grow in size as it got "closer". No support for rotation or textures, but the OP listed scaling as a hardware feature of interest and Star Ship certainly represents an early example of a machine that provided hardware assisted sprite scaling (with smoother control over scaling than many later machines, interestingly enough) for purposes of creating a "3d" effect. Interestingly, the cabinet also featured hardware-assisted circle drawing.

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