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Got a question about how the 68000 addresses memory.
Wikipedia says:

The 68000 has a 24-bit external address bus and two byte-select signals "replaced" A0.

Here is an image of the chip's pins:68000 pinout

As Wikipedia says, A0 is not there. So instead, we've got D0 thru D15, so that the CPU can fetch or store 16 bits at a time.

So what are the "byte-select" signals mentioned in the Wikipedia quote for?

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  • 3
    It might be interesting to mention that the "youngest" 68k derivate, the 68SEC000 CMOS version actually has an A0 on its address bus - It can operate in both 8 and 16-bit data bus mode. Otherwise (ignoring that as a CMOS device it can run in full static mode), it is a full replacement for the 68000 CPU.
    – tofro
    Jun 5 '17 at 12:36
  • 68000 program fetch had to be aligned, opcodes may only start on even addresses (because of the missing A0). Branches, jumps or vectoring to odd addresses will throw an exception. But for data access (especially with memory mapped I/O) a bytewise, unaligned access is inevitable and lead to the LDS/UDS signals solution. Jun 19 '17 at 1:00
  • Also 68008 had 8-bit bus, which simplified this issue.
    – jonathanjo
    Nov 29 '18 at 17:34
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The byte select signals select the low byte or the high byte or both. The 68000 has instructions for reading or writing words (16 bits) and bytes. In the latter case, it needs to be able to tell the world which half of the databus it is reading or writing.

According to the 68000 user manual (table 3-1), when the process is reading or writing the data bus the LDS and UDS signals are used to tell the world which byte or bytes the processor is trying to read/write. This means that you can connect devices with 8 bit ports to the databus and not have spurious reads and writes to the wrong ports.

Also, it means the 68000 can write a single byte to memory. If you want to execute

mov.b d0,someAddress

you put the low byte of d0 on either the low byte or high byte of the databus depending on whether someAddress is even or odd respectively, but you don't want the memory to store the other byte of the databus as well. The byte select signals can stop it from doing that.

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  • @ColeJohnson No it's table 3-1 on page 3-5.
    – JeremyP
    Oct 12 at 7:43
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The signals are there so in byte addressing mode the 68000 can read and write individual bytes.

From memory UDS means that valid data is on bits 8..15 of the data bus and LDS means that valid data is on bits 0..7 of the data bus.

In contrast a 8086 family part calls LDS A0 and BHE for the other bits. In practice on an AT architecture machine this is a little different as the hardware can map 16 bit accesses into two 8 bit ones for compatibility with original PC hardware.

This is particularly important as the 68000 maps peripherals into memory. So you might not want to do a 16 bit read / write cycle.

When I get home with a bit of time and some datasheets I'll try and expand this a bit (particularly how the AT bus works) and make sure I have the UDS/LDS mapping to bits correct

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  • On little-endian systems, the actives states of an /LDS/UDS pair would mirror those of A0-/BHE pair. 00 for word access, 01 for first-byte access, and 10 for second-byte access. It's not intuitive that the idle state for a pair called A0-/BHE pair should have A0 set, however, and the A0-/BHE naming wouldn't really make sense on a big-endian system.
    – supercat
    Feb 15 '19 at 17:44
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As others have explained this pin allows the 68000 to select an individual byte to read/write rather than a 16 bit word. However, they haven't explained why it was designed this way.

The 68k was designed for a 16 bit bus, with 16 bit RAM and ROM and peripherals. Byte addressing is not used with such a system, the smallest addressing unit is a 16 bit word. If the 68k wants to read/write a byte it handles it internally, e.g. reading a word and discarding 8 bits.

This technique is problematic for 8 bit peripherals. A read operation can have consequences as some parts alter their state on a read, e.g. a FIFO, so having to read an unrelated register or do a read-modify-write cycle would make the 68000 incompatible with them. The solution was the byte select pin, which acts as an additional address pin for 8 bit devices on the bus.

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  • Even without upper/lower byte selects, 8-bit peripherals may be handled on a 16-bit bus by simply having them use one byte out of each word and ignoring the other one. The bigger issue is with RAM where one might want to write the upper byte, lower byte, or both.
    – supercat
    Feb 15 '19 at 17:36
  • @supercat the issue with that is that it doubles the address of every register in the peripheral, and the programmer needs to adjust their code. It's possible to do but very annoying and error-prone.
    – user
    Oct 14 at 14:43
  • Adjusting the code is a bit annoying, but allowing dynamic switching of memory bus size requires adding additional hardware in both inside and outside the CPU. That may be worthwhile when designing a chip to be compatible with an earlier design that had an 8-bit bus, but the 68000 was an all new design.
    – supercat
    Oct 14 at 14:48
  • @supercat it's literally just a couple of 8 bit buffers with the OE line one one inverted.
    – user
    Oct 15 at 15:36
  • Things could be implemented somewhat simply if it would be acceptable to regard attempts to perform a 16-bit read/write from an 8-bit address as a bus fault, but even if the chip included logic to support use of an 8-bit bus for 8-bit operations only, treating 16-bit operations on 8-bit addresses as a bus fault, one would still need external hardware to let the CPU know when to fetch odd-address data from the same side of the bus as even-address data. Unless one needs compatibility with software written for an 8-bit bus, it's cheaper just to have I/O registers occupy every other address.
    – supercat
    Oct 15 at 17:05

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