Is there a comprehensive description of the Electrologica X1/X8 instruction set?

Question

The Electrologica X1, and its successor X8 were word-based computers with 27-bit words, using 1's complement binary arithmetic. In an article comparing Algol-60 compilers for X1 and X8 F. E. J. Kruseman Aretz gives (p. 21) a short summary, albeit very informative for most purposes, of the instruction set of X1, a terse resumé of which is:

Each instruction occupied exactly one word, and in most instructions the least-significant 15 bits were used either as an address or a literal, depending on the addressing mode.

The remaining 12 bits were subdivided into

• 6 bits of the "opcode proper" (ocp),
• 2 bits for the addressing mode (0 - access the memory word referred by the address field, 1 - use the address field as a literal, if it makes sense for the given instruction, 2 - add contents of the register B, for "base", to the address field to find out the effective memory address, 3 - not mentioned, another source tells that it was used for self-modifying code),
• 2 bits for the condition code generation (0 - do not generate, 1 - "the result is >= +0", 2 - "the result is +0/-0", 3 - "the sign of the result is equal to that of the previous condition-generating result"),
• 2 bits for the conditional execution (0 - unconditional, 1 - execute but do not modify the target, 2 - skip if the condition is false, 3 - skip if it is true)

The opcode proper further subdivided into two 3-bit parts, "register" and "function".

The article stops at providing details to figure out of all mentioned instructions. For example,

For transfer of control there are a.o. the following instructions:

ocp ELAN notation effect                                  variants
40  JUMP(label)   T:= T + store[label]                    UYN :B
41  JUMP(−label)  T:= T − store[label]                    UYN :B
42  GOTO(label)   T:= store[label]                        UYN :B
42  GOTOR(label)  restore T,C,LS,OF,... from store[label] UYN B
46  SUB0(:label)  store[8]:= T,C,LS,OF,... ; T:= label    UYN
... ...           ...                                     ...
46  SUB15(:label) store[23]:= T,C,LS,OF,... ; T:= label   UYN

Herein is T the instruction counter. Also in these instructions T is incremented by 1 before execution of the instruction.

Which bit patterns in the actual binary representation of the instruction with ocp 42 allowed to tell apart GOTO from GOTOR is unclear; the same stands for ocp 46 SUBn.

Another case of superficiality for the sake of brevity is

An important group are the 16 shift operations. There are four different circuits: A, S, AS, and SA. The circuit AS has 53 bits (the sign bit of S is excluded from the shift) and plays a role in arithmetical shifts, the circuit SA has 54 bits. There are also 2 kinds of shifts: round shifts, in which the bits that are shifted out at one side are entered again at the other side, and shifts–out, where bits are lost at one side and copies of the sign bit are supplied at the other side. Both shift types can, finally, be carried out to the right and to the left.

No indication of the ocps of these instructions, or of other ways to encode the shift circuit, type and direction, is given.

Is there a comprehensive table of all of the valid opcodes of Electrologica X1 and their meanings?

Answer 1

I can give you my tables for the X1, if that helps. I didn't keep track from where I compiled them exactly. Looking over it again, most seems to come from Dijkstra's PhD Thesis [1].

The binary encoding is actually specified in Appendix 2, p. 134ff.

For m in 4T and 6T, the 3 lower significant bits are in bits 21 to 19 of the order, and the remaining bit for 6T is in bit 18.

The P command decoding is given in a table on p. 135.

And the GOTOR is the P-version if the normal 2T order (p. 17)

---

Registers (Dutch abbrev)

A  27 bits  acc
S  27 bits  acc
T/OT 15 bits  order counter
OR 27 bits  instruction register
B  15+1 bits  15 address + 1 sign  (address offset)
C  1 bit  condition
C' 1 bit  sign of result of last condition setting operation
OF 1 bit  overflow

(n) contents of memory
(A) contents of register

---

Order

27 bits, 26 .. 0

26-15  12 bit function
26-21    6 bit from function number + letter(s)
26-24      3 bit letter
23-21      3 bit function number
20-19    2 bit from address modification
18-17    2 bit from condition setting
16-15    2 bit from condition reaction
21-19    3 bit m in 4T, 6T
18       1 bit m (MSB) in 6T
14-0  15 bit address

(Thesis Appendix 2, p. 134)

letter: upper 3 bit

A = 0
S = 1
X = 2
LA = 2.5
D = 3
LS = 3.5
B = 4
T = 5
Y = 6
Z = 7

Note that the LA and LS use the high bit from the function number, hence ".5".

- = 00
A = 01
B = 10
C = 11

- = 00
P = 01
Z = 10
E = 11

- = 00
U = 01
Y = 10
N = 11

Assembler columns:

0 Condition  U Y N
1 Function digit + letter(s)
2 Line number
3 First paragraph letter
4 Second paragraph letter, followed by page number
5 Address modification  A B C
6 Condition setting  P Z E

For R in A,S,B:

0R n    (R) + (n) -> (R)
1R n    (R) - (n) -> (R)
2R n        + (n) -> (R)
3R n        - (n) -> (R)
4R n    (n) + (R) -> (n)
5R n    (n) - (R) -> (n)
6R n        + (R) -> (n)
7R n        - (R) -> (n)

For R in A, S:

0LR n   +(n) OR (R) -> (R)
1LR n   -(n) OR (R) -> (R)
2LR n   +(n) AND (R) -> (R)
3LR n   -(n) AND (R) -> (R)

0X n    (A) + (n) * (S) -> (AS)
1X n    (A) - (n) * (S) -> (AS)
2X n        + (n) * (S) -> (AS)
3X n        + (n) * (S) -> (AS)

0D n    (AS) / +(n): rem -> (A), quot -> (S)
1D n    (AS) / -(n): rem -> (A), quot -> (S)
2D n    (A) * 2^26 / +(n): rem -> (A), quot -> (S)
3D n    (A) * 2^26 / -(n): rem -> (A), quot -> (S)

0T n    (T) + (n) -> (T) ; stop if (n) <= -0            ; jump relative
1T n    (T) - (n) -> (T) ; stop if (n) <= -0            ; jump relative
2T n        + (n) -> (T) ; stop if (n) <= -0            ; jump absolute
4T n m  (m) - 1 -> (m); (n) -> (T) ; 0 <= m <= 7        ; decrement and loop
6T n m  (T) -> (m+8) ; n -> (T) ; 0 <= m <= 15          ; subroutine


MUL: (n) * S -> A | S
DIV: A | S / (n) -> quot S, rem A

Shifts

P = special combination of Y and Z
  (Dijkstra doesn't give details)
  no U version, no A version
  B and C can be applied with care (overflow)
  P Z E does apply to A for AA/AS, and S for SS/SA

0P  Round shift to the left
1P  Round shift to the right
2P  Clear shift to the left
3P  Clear shift to the right

4P  register transport   (R) -> (R')
5P  register transport  -(R) -> (R')

6P AA normalize
6P SS normalize
6P AS normalize

7P stop

I/O in

0Y n    (A) + (..) -> (A)
1Y n    (A) - (..) -> (A)
2Y n        + (..) -> (A)
3Y n        - (..) -> (A)

0Z n    (S) + (..) -> (S)
1Z n    (S) - (..) -> (S)
2Z n        + (..) -> (S)
3Z n        - (..) -> (S)

I/O out

6Y n        + (A) -> (..)
7Y n        - (A) -> (..)

6Z n        + (S) -> (..)
7Z n        - (S) -> (..)

1 XP in = tape reader
1 XP out = tape punch

2 XP in = typewriter echo
2 XP out = typewriter

Address modification: (see Dijkstra's PhD thesis for best description)

- reference. n is interpreted is addr, (n) is acted on
A "absolute": immediate, use n instead of (n), expand with 0s to 27bit.
B B-correction: indexed, use (n+B) instead of (n).
C C-correction: pre-incremented, use (n+B) instead of (n), replace n in instruction with n+B.
  self-modifying code, only works for instructions in "living memory" (RAM).

Condition modification

Y yes-condition = only execute if C affirmative
N no-condition = only execute if C negative
U undisturbed = don't transfer result to destination

Condition Setting

P positive
Z zero
E equal signs

I/O

Interrupt

6 groups no limit for units in groups

[1] https://www.cs.utexas.edu/~EWD/PhDthesis/PhDthesis.PDF