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My simplified understanding of the evolution of the Intel processors over the last 20 years is that the Pentium II and Pentium III architectures were sort of "dead-ends", and today's Intel processors were built on an earlier design introduced with the Pentium (P5) in the early-90s. My understanding is the P5 core was enhanced to support the x86-64 instruction set "borrowed" from AMD and multi-threading, and they went to multiple cores on die.

I am looking for validation or correction of my (obviously simple) understanding here, as well as more details on the hows & whys for Intel to pursue this strategy? Additionally, why were the PII/PIII approaches a "bust"?

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    Quick corrections: the dead-end was the Pentium 4 NetBurst architecture. Current Intel CPUs are remote descendants of the Pentium III and initial Pentium M, apart from the Xeon Phi which is a descendant of the original Pentium (at least in its current incarnation, Knights Corner). Sandy Bridge and Haswell introduced significant changes, hence the “remote” above. – Stephen Kitt Jul 25 '17 at 16:24
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    Actually Knights Corner isn’t the current incarnation of Xeon Phi. – Stephen Kitt Jul 25 '17 at 16:33
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    The question is incorrect: the true revolution was Pentium Pro, which translates CISC instructions to an internal out-of-order RISC machine. All our Intel processors today are descendants of Pentium Pro. Pentium Pro was offered to consumer space in the form of Pentium II, and later, Pentium III. The dead end was Pentium 4. Pentium Pro is the processor that effectively killed RISC (except as an internal implementation of CISC processor, and in some niches like smartphones). – juhist Jul 26 '17 at 14:07
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    @juhist - I don't think smartphones are a 'niche' - in server space, sure, but, while it's hard to find exact numbers, I'd bet there are more smartphones in use right now than desktops and laptops combined. (Even though I have 4 desktops / laptops in active use and only one phone). – Jonathan Cast Jul 26 '17 at 17:55
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    @juhist: The success of x86 is more an accident of history than an argument against RISC as a concept. There are frequent arguments about whether x86 gains more from compact code-size (more L1I-cache hits) than it loses from the complexity of decoding x86 instructions (power and transistor costs) and quirks of the ISA (extra mov instructions because of 2-operand destructive instructions, and also weird stuff like variable-count shift instructions have to preserve flags if the count is zero, so there's a false dependency on input flags). The "x86 tax" is a real but small cost on CPU designs – Peter Cordes Jul 27 '17 at 2:11
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Intel x86 CPU Lineages

There are only a few Intel x86 CPU microarchitectural lineages. Each of these lineages starts with a processor design that was largely made from scratch, incorporating little of any previous CPU's design.

The early microarchitectural lineages were all dead ends. In this stage of x86 CPU design Intel came up with a new microarchitecture for each major new CPU version that completely replaced the old. They are:

  • The original 8086 design, also used largely unchanged in the 8088 and improved in the 80186.
  • The 80286 design, which added support for protected mode and a 16 megabyte address space
  • The 80386 design, which added support 32-bit code and a 4 gigabyte address space
  • The 80486 design, which significantly improved performance through pipelining.

After these processors Intel started to take a more incremental approach to microarchitecture design. Intel would only come up with a completely new design three more times, creating three more lineages of which only one is currently a dead-end:

  • The Pentium processor introduced the P5 microarchitecture which was improved on with the Pentium-MMX and much later resurrected to form the basis of the Atom and Xeon Phi CPUs. The major improvement in this design was superscalar dual pipelines. (Out-of-order execution was added in the Silvermont microarchitecture, but it appears that current Atom and Xeon Phi CPUs still belong to this lineage.)

  • The Pentium Pro introduced the P6 microarchitecture, starting the lineage that most Intel CPUs, including all current desktop and server CPUs, have used since. The Pentium II and Pentium III CPUs introduced further improvements of this design. The big improvement with the P6 architecture was out-of-order execution.

  • The Pentium 4 introduced the NetBurst microarchitecture. This lineage is a dead-end. While it was improved on during its lifetime, it's long been abandoned by Intel and not likely to ever be brought back to life like the P5 lineage. Its major improvement was a very long pipeline which allowed for a big jump in clock speeds, but hurt performance overall.

The Failure of NetBurst and the Pentium 4

The NetBurst microarchitecture was a failure for largely one reason, it was designed primarily to win the "megahertz wars". In 2000 Intel's main competitor in the x86 CPU market, AMD, was able to release a 1 GHz CPU before Intel could. Intel struggled to beat AMD. They released a 1.13 GHz Pentium III later that year but had to recall it, while AMD was able to push forward to 1.2 GHz.

The new NetBurst microarchitecture let Intel and its Pentium 4 CPUs take the megahertz crown decisively. Its much longer pipeline, double the length of the pipeline used in Pentium III, allowed Intel to consistently and significantly beat AMD in raw clock speed. However that came with a big and ultimately fatal penalty, longer pipelines meant a longer delay anytime the processor was forced to discard the contents of the pipeline. Intel hoped that better compilers would produce code tuned to the NetBurst architecture to minimize how often this occurred, but in practice this happened often enough in most code to completely offset the performance improvements gained by the faster clock speeds.

While being able to advertise faster CPU speeds gave a Intel an advantage over AMD in the desktop markets, the NetBurst design ended up hurting Intel significantly in the more lucrative server market. In the latter market, customers weren't as easily swayed by bigger gigahertz numbers, and even overall performance wasn't all they were interested in. They were also concerned about heat, wanting to pack as many CPUs as they could into their server racks without having to pay for bigger and more expensive cooling systems. On the performance-per-watt metric AMD's lower clocked CPUs were able to significantly beat Intel, and this helped AMD grab about a quarter of the server market at its peak.

The rise of the Pentium-M

While it took Intel a fairly long while before they realized the NetBurst microarchitecture was a dead-end, the fact that the power hungry Pentium 4 CPUs were a poor choice for laptops was obvious from the beginning. So they had a team of Intel engineers in Israel come up with a low power CPU design that would work well in mobile computers. Rather than base their design on the Pentium 4 they chose to base it on the already more power efficient, if not as fast, Pentium III CPUs. This resulted in the Pentium-M, a CPU that, while not clocked as fast as Pentium 4, could often beat it in real world performance while generating much less heat.

Around the end of Pentium 4 era the advantages of the Pentium-M were becoming obvious. While Intel only sold it as a mobile CPU for use in laptops and other similar applications, motherboard manufacturers and server makers were increasingly releasing products for desktops and servers applications that used Pentium-M CPUs. If Intel didn't kill off the NetBurst design, the market soon would prefer to buy AMD and Pentium-M CPUs instead.

While Intel was slow to respond to the threat of AMD or leverage the advantages of their own Pentium-M CPUs, they eventually got the message. First releasing a variant of the Core Duo for servers and then the Core 2 CPUs for both servers and desktops. These new more efficient CPUs were based on the Pentium-M. All Intel's desktop and server CPU designs since then are descended from the Pentium-M and so ultimately the Pentium Pro and its P6 microarchitecture. Of Intel's current CPU designs only Intel's Atom (low-power/performance mobile/embedded) and Xeon Phi (high-end compute engine) CPUs aren't P6 descendants.

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    There's also an interesting parallel with the ISAs: Intel bet everything on throwing away the x86 legacy cruft and starting from scratch with the IA-64 ISA for servers and workstations, but they married this ISA to the EPIC microarchitecture, which had similar problems to the NetBurst one: it was fast, but extremely power hungry. The EPIC microarchitecture bet heavily on speculative execution (i.e. executing both sides of a branch in parallel before you have computed the condition, then throwing one of the execution paths away), which in some benchmarks resulted in 80% of all energy … – Jörg W Mittag Jul 25 '17 at 21:44
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    … being spent on results that ended up being unused. This was simply not sustainable, especially after AMD managed to a) steer the focus from raw speed to power efficiency, and b) came up with a backwards-compatible 64 bit extension to the x86 ISA instead of a brand-new one like Intel did. As a result, Intel had to backpedal on both their successor to the P6 microarchitecture and their successor to the x86 ISA. – Jörg W Mittag Jul 25 '17 at 21:45
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    @RossRidge Even better, it allowed the same CPU to effectively become more powerful as the compilers improved, which seemed like a good idea at the time. In reality, making the CPU do these kinds of optimisations turned out far more effective - how often do you get a recompile of all your products? It wasn't all that common on Windows machines back then; how do you get the software developers to ship different optimised binaries for each different CPU? It also made newer, faster CPUs a lot more attractive. Intel bet on "smart enough compiler", and it turned out to be a bad bet. – Luaan Jul 26 '17 at 15:03
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    "how often do you get a recompile of all your products?" - Well, if you are running .Net or JVM, you do it every time a customer runs the product (or at the very least, every time they install it). In both cases, the JITter can generate the appropriate instructions depending on the customer's actual platform. – Martin Bonner Jul 26 '17 at 15:47
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    @PeterCordes Yah, I chose the word "lineage" deliberately to avoid the Ship of Theseus like question of when has a design been incrementally changed so much that it counts as an entirely new design. I also wanted to focus on the Pentium IV and Pentium-M while not getting bogged down in technical details. I thought about mentioning Sandy Bridge, but I felt it would just be distraction. – Ross Ridge Jul 27 '17 at 16:36
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My approximate version:

Prior to the Pentium, Intel CPUs were pipelined: different parts of the CPU would simultaneously be working on different operations, but the different parts were designed to work in sequence, with every operation proceeding through all parts.

The Pentium expanded on that by being superscalar. Rather than there being only exactly one instruction at each stage of execution at any given time, for a certain period there are two pipelines — one that can perform any defined operation and one that can perform only the simpler operations. If two instructions are independent and can be dispatched down different pipes then they will be.

The Pentium Pro expands on that by introducing out-of-order execution. Rather than only two pipes, with instructions being considered for potential parallel execution in the order they come, there are a bunch of slots for incoming instructions. An instruction that has no remaining preceding dependencies then proceeds through an execution path, its slot being taken by the next instruction in the stream. That way the Pentium Pro can potentially perform three instructions simultaneously, and is more likely to do so than if it required that all three be sequential and independent.

(Core2 and later widened the pipeline to a width of 4 instructions. Actually decoded uops, so complex instructions take more slots. Skylake can decode more than 4 instructions per cycle, but the narrowest bottleneck (issue/rename) is still only 4 uops wide. Wider decode helps avoid bubbles in the pipeline by making up for cycles where the front-end decoded fewer instructions.)

Keeping it broad, the Pentium III and IV mostly just widen that same process, with a few additions. Hyper threading is an obvious one — if you pretend to have more cores then you'll be handed multiple execution threads at once. So it's more likely you'll find suitable independent instructions, and be able to use more of your execution units at once.

There's a problem though: it's now a branching thing with a few places where you might wait a while, but a processor is still a pipeline. Instructions enter at one end, go through n intermediate steps, then finally are considered done. But what happens if there's a branch? In the worst case, if the processor is currently working on m instructions and a branch occurs, it needs to throw away all the work it did on m-1 of them, then start refilling its pipeline from the point of entry, with the various stages after fetching being empty until something new flows into them. That's called a pipeline stall. Making predictions about branches based on their recent history helps to avoid stalls (as you've hopefully guessed which set of instructions will come next correctly and if you did then there's no need to flush), and speculative execution (giving some resources to the path you don't expect to be taken to hedge your bets) help but are not ideal.

The Pentium IV took a misstep in gambling on a really long pipeline. The thinking was that a longer pipeline has a greater cost when a stall occurs but gives small, simple individual parts, which are easier to scale up the clock rate on. So what you lose on stalls you more than gain on throughput.

Unfortunately, increasing the clock also increases the heat output, and process improvements didn't turn up to quickly enough to correct for that. So it was difficult to scale, and the gamble didn't pay off.

So Intel switched back from the microarchitecture they'd picked for the Pentium IV to the much-developed version of that which had originated in the Pentium Pro, and doubled down on instruction set extensions (both improving the vector stuff and the 64-bit transition, though the switch back put the latter temporarily on hold) and parallelism as software-side drivers of processing improvements, to bolster incremental improvements to each core.

But what they've definitely abandoned is a long pipeline and the expectation of process improvements driving clock speed improvements.

So: the original Pentium was superscalar, which is a stepping stone, but modern Intel CPUs have a philosophy descended most directly from the Pentium Pro and its out-of-order design. The Pentium IV's architecture relied on a misprediction of manufacturing technology and was a bit of a dead end.

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    +1. Understanding the instruction pipes and execution units is key to understanding the design and history of Intel CPUs IMO. I find it interesting to see some ideas which were implemented too soon coming back once the processes are refined (e.g. hyper-threading, branch prediction, and even somewhat longer pipelines in recent microarchitectures), and Intel’s back-and-forth on some design choices (split caches, micro-op instruction caches, branch prediction implementations...). – Stephen Kitt Jul 25 '17 at 16:58
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    There’s another side of things which is the energy management; Pentium 4 was all about keeping all the silicon running and in-use (hence hyper-threading), the return to the Pentium III design with the Pentium M was all about using silicon as efficiently as possible. But it’s hard to avoid post-facto rationalisations here; after the Pentium 4, Intel just needed a working CPU design which wouldn’t be a dead-end, and oh look, this team in Israel happened to be working on something which looks sensible... – Stephen Kitt Jul 25 '17 at 17:01
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    Actually, earlier CPUs were not pipelined. The 486 was Intel's first with a real pipeline. The Pentium extended that considerable to superscalar IPC - however, it was the last in-order native x86 core (until the Atom much later which directly succeeded the P55C), the Pentium Pro and all later cores are out-of-order, heavily pipelined RISC cores with a x86 instruction decoder frontend. – Zac67 Jul 25 '17 at 17:33
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    @StephenKitt The Pentium-M has been out for two or three years when Intel first started produce versions for the desktop and server markets. By the time Intel realized that the Pentium 4's NetBurst architecture was a dead end the team in Israel had already finished and shipped their more sensible design. – Ross Ridge Jul 25 '17 at 17:35
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    @mnem The P4 was considered by many to be idiotic even at the time. It was seen by many as a flagrant attempt to push up clock speeds at the expense of real performance. At the time, they were in a battle with AMD to see who could advertise the highest clock speed. since that was an easy number to market. – JeremyP Jul 26 '17 at 8:55
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Pentium 4 (NetBurst uarch-family) was Intel's dead-end misadventure between the original Pentium Pro / PII / PII (P6 uarch) and its current mainstream CPUs.

Intel had hoped to clock P4 much higher, above 5GHz I think. But smaller transistors didn't lower power consumption as much as they'd hoped, so they were just generating the same amount of heat in an even smaller area, making it even harder to cool. (See also the "power wall" and "brainiac vs. speed-demon" sections of this article.)

Power density is now a major issue for CPUs, even when going for pure performance (rather than laptop battery life). They have to not melt, and unless you're going to use diamond as a thermal conductor between CPU and heat sink, it's hard to get much more heat out of a CPU. Saving power by turning off temporarily unused circuits is a big part of why current CPUs can clock so high. See also https://en.wikipedia.org/wiki/Dark_silicon.


Following P4, Intel produced Pentium-M, Core2, and Nehalem, all of which were direct descendants of Pentium III and members of the P6 microarchitecture family.

Sandybridge: enough under-the-hood changes to be called a new microarchitecture family

Sandybridge is generally considered to be the first member of a new microarchitecture family (which includes Intel's current Skylake/Kaby Lake mainstream microarchitecture), but it's not a completely new design. David Kanter's detailed article about Sandybridge says:

The Sandy Bridge CPU cores can truly be described as a brand new microarchitecture that is a synthesis of the P6 and some elements of the P4.

The Sandybridge-family of microarchitectures definitely has P6 ancestry, but it's not still part of the same family. Nehalem/Westmere is generally considered the last mainstream member of the P6 family.

Sandybridge kept some parts of Nehalem essentially unchanged. The latencies and throughputs of many instructions are the same as on Nehalem, and even run on the same ports (see Agner Fog's microarch pdf) so it's likely that a lot of the execution units are not significantly different.

The P4 side of its ancestry is more in the form of ideas than actual blocks of logic. A good example of taking just the idea but with a different implementation is Sandybridge's decoded-uop cache. It avoids the power cost and throughput bottleneck of re-decoding x86 instructions when the same code runs repeatedly, but it's very different from P4's trace cache. (And unlike P4, SnB still has good decoders, so uop-cache misses are not terrible.)

Another P4 feature that SnB uses is a physical register file instead of keeping uop input/output values in the ROB directly. SnB's internal uop format was reportedly simplified relative to P6, so all of the internals of the out-of-order core have changes from Nehalem. SnB is much more closely related to P6 than P4, but is definitely not just another member of the P6 family.

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    Yes indeed. Sandy Bridge feels a lot like the designers thought “let’s take a look at all the ideas we thought were cool in the P4 days, and see if we can re-do them better with all that we’ve learnt since then”. – Stephen Kitt Jul 27 '17 at 15:06
  • Sandy Bridge was an incredible jump in IPC (single thread performance at the same clock): from Nehalem to Sandy Bridge is about the same as Sandy Bridge to Kaby Lake! About 20%. – chx Jul 27 '17 at 20:48

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