My approximate version:
Prior to the Pentium, Intel CPUs were pipelined: different parts of the CPU would simultaneously be working on different operations, but the different parts were designed to work in sequence, with every operation proceeding through all parts.
The Pentium expanded on that by being superscalar. Rather than there being only exactly one instruction at each stage of execution at any given time, for a certain period there are two pipelines — one that can perform any defined operation and one that can perform only the simpler operations. If two instructions are independent and can be dispatched down different pipes then they will be.
The Pentium Pro expands on that by introducing out-of-order execution. Rather than only two pipes, with instructions being considered for potential parallel execution in the order they come, there are a bunch of slots for incoming instructions. An instruction that has no remaining preceding dependencies then proceeds through an execution path, its slot being taken by the next instruction in the stream. That way the Pentium Pro can potentially perform three instructions simultaneously, and is more likely to do so than if it required that all three be sequential and independent.
(Core2 and later widened the pipeline to a width of 4 instructions. Actually decoded uops, so complex instructions take more slots. Skylake can decode more than 4 instructions per cycle, but the narrowest bottleneck (issue/rename) is still only 4 uops wide. Wider decode helps avoid bubbles in the pipeline by making up for cycles where the front-end decoded fewer instructions.)
Keeping it broad, the Pentium III and IV mostly just widen that same process, with a few additions. Hyper threading is an obvious one — if you pretend to have more cores then you'll be handed multiple execution threads at once. So it's more likely you'll find suitable independent instructions, and be able to use more of your execution units at once.
There's a problem though: it's now a branching thing with a few places where you might wait a while, but a processor is still a pipeline. Instructions enter at one end, go through n intermediate steps, then finally are considered done. But what happens if there's a branch? In the worst case, if the processor is currently working on m instructions and a branch occurs, it needs to throw away all the work it did on m-1 of them, then start refilling its pipeline from the point of entry, with the various stages after fetching being empty until something new flows into them. That's called a pipeline stall. Making predictions about branches based on their recent history helps to avoid stalls (as you've hopefully guessed which set of instructions will come next correctly and if you did then there's no need to flush), and speculative execution (giving some resources to the path you don't expect to be taken to hedge your bets) help but are not ideal.
The Pentium IV took a misstep in gambling on a really long pipeline. The thinking was that a longer pipeline has a greater cost when a stall occurs but gives small, simple individual parts, which are easier to scale up the clock rate on. So what you lose on stalls you more than gain on throughput.
Unfortunately, increasing the clock also increases the heat output, and process improvements didn't turn up to quickly enough to correct for that. So it was difficult to scale, and the gamble didn't pay off.
So Intel switched back from the microarchitecture they'd picked for the Pentium IV to the much-developed version of that which had originated in the Pentium Pro, and doubled down on instruction set extensions (both improving the vector stuff and the 64-bit transition, though the switch back put the latter temporarily on hold) and parallelism as software-side drivers of processing improvements, to bolster incremental improvements to each core.
But what they've definitely abandoned is a long pipeline and the expectation of process improvements driving clock speed improvements.
So: the original Pentium was superscalar, which is a stepping stone, but modern Intel CPUs have a philosophy descended most directly from the Pentium Pro and its out-of-order design. The Pentium IV's architecture relied on a misprediction of manufacturing technology and was a bit of a dead end.
movinstructions because of 2-operand destructive instructions, and also weird stuff like variable-count shift instructions have to preserve flags if the count is zero, so there's a false dependency on input flags). The "x86 tax" is a real but small cost on CPU designs