Any accelerator for the Amiga work by disabling the CPU and taking over the complete bus system to become the bus master.
To accomplish this, a low level signal must be applied by the accelerator to pin
BR (Bus Request). The CPU will answer asserting pin
BG (Bus Grant). After the accelerator receives this signal, it acknoledges it by asserting
BGACK. When all of this happen, the original CPU electrically disconnects itself from the system bus, leaving the accelerator to take over it. The accelerator has a new CPU with its own clock circuitry, maybe some RAM mapped outside the normal address space of the 68000, and some glue logic to talk to a 16 bit data bus (accelerators usually are true 32-bit CPUs, so a way to serialize a 32-bit memory access to two sequential memory accesses is needed) so all custom chips think they are still talking with the 68000.
BGACK signals are wired-AND signals. This means that their default state is high (logic 1) but any logic 0 input applied to them makes the signal to go down, as if the output was driven by the AND logic operation of all wires connected to it.
The adapter that plugs on the top of the 68000 in the Amiga 600 allows the accelerator to access to all CPU signals. One of them will be
BR, so when the accelerator wants to take over control, it simply put a logic 0 on it, starting the above mentioned bus relinquishment operation.