The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples:
Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes, though no implementation was regarded as correct. The inconsistencies did not affect ordinary use of the PDP-11.
My semi-recollection/semi-guess is that the differences could be due to variations in micro-programs dealing with auto-increments or auto-decrements of registers when a memory access interrupt occurred.
Can anyone shed light on these "subtle differences"?
The fact that no implementation was regarded as correct deserves another question: was there another instruction set architecture with similar inconsistencies without an officially declared correct way of implementing the architecture?
The answer to the stricken question is likely negative; as there is no way to prove a negative except by exhaustive research, and I wouldn't want to have a virtually unanswerable question under my name, I will not post it separately, unless someone would want to answer it positively.
A contemporary example would be a difference between Intel and AMD in their handling of a jump instruction with a data size override prefix (punchline at 32m50s).