The wiki page PDP-11 architecture has a cryptic paragraph with no
references or examples:
Over the life of the PDP-11, subtle differences arose in the
implementation of instructions and combinations of addressing modes,
From Bitsavers the PDP-11 Systems Handbook 1987, Appendix A-PDP-ll Family Differences Table states:
The table that follows illustrates the issues involved in software
migration between different members of the PDP-ll family.
This table starts with base model processors from the PDP-11's line of second generation processors (e.g. PDP-11/05) through to the early VAX systems (e.g. VAX-11/7xx series). All these processors were microprogrammed implementations of the PDP-11 instruction set. Note: only the first generation PDP-11/20 was not microprogrammed and this processor is not included in this Appendix.
The table occupies 15 pages of the manual and is broken down into the following topics:
- Instructions or Instruction Sets (5 Pages)
- Memory Management and Relocation (2 Pages)
- Interrupts (1 Page)
- Buses (1 Page)
- Processor Status Word (2 Pages)
- General Purpose Registers (1 Page)
- Error Handling (2 Pages)
- Consoles and Serial Ports (1 Page)
Each member of the family has some small difference in the way it
The instruction set implemented on a particular site would be dependent on processor model number as well as the processor options fitted. There was:
Extended Arithmetic Element (EAE) e.g. KE-11A
Floating Instruction Set (FIS) e.g. KE11-F
Floating-Point Processor (FPP) e.g. FP-11A
Commercial Instruction Set (CIS) or Extended Instruction Set (EIS)
For the PDP-11 the memory bus could be 16, 18 or 22 bits wide therefore the amount of physical memory that an assembly language program could address varied significantly.
Therefore moving an assembly language program between systems could be a problem. If the assembly language program was limited to the Basic Instruction Set then the differences were small.
Therefore you might want to question the statement that there were only subtle differences when the differences were described by a 15 page table.
Any program developed using PDP-ll operating systems with higher level
languages will migrate from one system to another with very little
Missing instructions could be emulated by the systems so there was only a speed penalty. For the majority of high level applications migration could be accomplished with little difficulty.
though no implementation was regarded as correct.
The Appendix A simply stated that "each member of the family has some small differences in the way it execute instructions." No processor was identified as having the 'correct' version. Therefore no implementation was regarded as correct.
My semi-recollection/semi-guess is that the differences could be due
to variations in micro-programs dealing with auto-increments or
auto-decrements of registers when a memory access interrupt occurred.
Can anyone shed light on these "subtle differences"?
The Appendix A table identifies which systems incremented addresses by one or two./
The fact that no implementation was regarded as correct deserves
another question: was there another instruction set architecture with
similar inconsistencies without an officially declared correct way of
implementing the architecture?
The answer to the stricken question is likely negative; as there is no
way to prove a negative except by exhaustive research, and I wouldn't
want to have a virtually unanswerable question under my name, I will
not post it separately, unless someone would want to answer it
There were a number of manufacturers that offered systems configured with writable microprogram storage. In the IBM 360/40 the additional microcode could add additional instructions that emulated the IBM 1400 series. The DEC VAX-11/750 had a writable User Control Store option that allowed custom instructions to be implemented