22

The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples:

Inconsistent instructions

Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes, though no implementation was regarded as correct. The inconsistencies did not affect ordinary use of the PDP-11.

My semi-recollection/semi-guess is that the differences could be due to variations in micro-programs dealing with auto-increments or auto-decrements of registers when a memory access interrupt occurred.

Can anyone shed light on these "subtle differences"?

The fact that no implementation was regarded as correct deserves another question: was there another instruction set architecture with similar inconsistencies without an officially declared correct way of implementing the architecture?

The answer to the stricken question is likely negative; as there is no way to prove a negative except by exhaustive research, and I wouldn't want to have a virtually unanswerable question under my name, I will not post it separately, unless someone would want to answer it positively.

A contemporary example would be a difference between Intel and AMD in their handling of a jump instruction with a data size override prefix (punchline at 32m50s).

6
  • 1
    I would suggest posting your second question as a second question.
    – user
    Commented Sep 6, 2017 at 6:22
  • @MichaelKjörling It will make sense splitting them as soon there is a concrete example of what exactly it asks about (cf. "similar inconsistencies") in the form of an answer to the first question.
    – Leo B.
    Commented Sep 6, 2017 at 7:18
  • THe only 'inconsitency' I can think of are extensions (like FP, etc) that have been only available on certein machines - and unlike the PC development, not enhanced machiens where sold for decades after. Same goes for certein instructions and their behaviour on muti processor memory, depending on the momory implementation. But thats (mostly) restricted to I/O access.
    – Raffzahn
    Commented Sep 6, 2017 at 7:59
  • Review the Wikipedia entry for IBM System 360 for differences between implementations of the hardware.
    – PDP11
    Commented Feb 7, 2020 at 5:19
  • @PDP11 A customary courtesy is to provide a clickable URL.
    – Leo B.
    Commented Feb 7, 2020 at 9:02

5 Answers 5

17

Here is an example:

mov r5,-(r5)

That moves the contents of R5 to the address location specified in R5 after first decrementing R5. The question is what gets put in the memory location? Is it the contents of R5 before the instruction was started or is it the decremented R5.

For example, if R5 contained 10 (decimal), usually the microcoded PDP-11s, would put 10 in location 9. Others, the earlier non microcoded ones, would put 9 in location 9.


Source: The book PDP-11 Architecture Handbook, 1983, digital, verifies this in Appendix B, "PDP-11 Family Differences". Specifically, the models 23/24, 15/20, 25/40, 60, J-11, and T-11 would pre-decrement r before using it. The 44, 04, 34, LSI-11, 05/10, 45, 70, and VAX would not.

10
  • Interesting, makes sense. Is there a chance you could add some source for further reading?
    – Raffzahn
    Commented Sep 6, 2017 at 8:57
  • 2
    That example comes from github.com/gaojiechina/os_collection/wiki/PDP-11-architecture
    – JeremyP
    Commented Sep 6, 2017 at 9:00
  • 1
    Now that's interesting. The page you linked is a verbatim copy of the Wiki artikle about the PDP architecture from 2014 - but exactly that paragraph got removed in 29015, as 'just guesses' and quite frankly, a change that important would break many programms, while the paragraph before mentioned that 'normal programs are not affected'. See here en.wikipedia.org/w/…
    – Raffzahn
    Commented Sep 6, 2017 at 9:10
  • 1
    Would be great if there are any, as this one seams to be not verified. I just went thru the manuals for the PDP11/20 (KA11 non microprogram) and 11/45 (KB11 microprogrammed) and couldn't find any hint. Same on the 1975 programming card. One would expect to find some when the difference is that obvious.
    – Raffzahn
    Commented Sep 6, 2017 at 10:02
  • 6
    The book PDP-11 Architecture Handbook, 1983, digital, verifies this in Appendix B, "PDP-11 Family Differences". Specifically, the models 23/24, 15/20, 25/40, 60, J-11, and T-11 would pre-decrement r before using it. The 44, 04, 34, LS1/11, 05/10, 45, 70, and VAX would not.
    – RichF
    Commented Sep 6, 2017 at 14:01
10

As I remember, there were the following inconsistensies:

  • Jumping to an odd address could bring different results (trap or continuing from the closest even address)

  • Byte operations with the stack pointer. In some models this would be working as with any other register, decrementing/incrementing SP by one, in others only increment/decrement of SP by 2 was possible.

  • Byte move to a register on some models would fill the other byte of the register with sign.

  • Different behavior of some SWAB and bit mask operations, I do not remember details.

5
  • 1
    re continuing from the closest even address - which is closer to address 12345 -- 12344 or 12346? :-) As far as I recall on the 11/24, the low bit was ignored, i.e., it would be 12344. This was widely seen as an annoying misfeature, since some bugs would not be detected.
    – dave
    Commented Jan 6, 2022 at 0:54
  • Again as far as I recall - byte move to a register always sign-extended. This sticks in my mind because I almost never wanted it to.
    – dave
    Commented Feb 3 at 15:35
  • 'Trap' was correct before the last edit. It's an "odd address trap" (because synchronous with instruction execution), not an interrupt (because not caused by an external signal). See page 128 in this handbook.
    – dave
    Commented Feb 3 at 17:41
  • @dave OK, revert
    – Anixx
    Commented Feb 3 at 18:39
  • Intel usage irritates me - the INT instruction is a trap, not an interrupt :-)
    – dave
    Commented Feb 3 at 19:40
8

Some PDP-11 family computers could address its own registers as the top 8 (16-bit) addresses in its address space. (The top 4 kwords were sometimes dedicated to an I/O page.) For example, a program running on the 05/10 model could place a short loop in R2 to R5 and execute it from those registers. On most models, however, accessing those locations would yield a time-out.

The above is item 7 in a 52-member list of architecture instructional differences within the PDP-11 family, as itemized in Appendix B, "PDP-11 Family Differences" of_PDP-11 Architecture Handbook, 1983, digital. Most are quite minor or obvious, such as some PDP-11s had the Extended Instruction Set (EIS) or floating point and some did not.

8
  • Differences of the kind "a program works on one platform and causes a bus error or an illegal instruction exception on another" are anything but subtle. Are there other items in the list similar to the one above?
    – Leo B.
    Commented Sep 6, 2017 at 15:46
  • 3
    @LeoB. Yes. For example the 4th listed variance is the behavior of JMP (R)+ (as well as JSR (R)+). On some models the register would be incremented by two first, whereas other models would immediately jump to the given value of R. I checked to see if I could find a copy of this book online, but I could not find it.
    – RichF
    Commented Sep 6, 2017 at 16:36
  • 2
    FWIW, MACRO-11 would flag the instructions that are known to cause different behaviour (error code Z), see MACRO-11 Lang Ref Manual. Commented Sep 6, 2017 at 17:47
  • 2
    @RichF You may want to move your comment about JMP (R)+ to the answer.
    – Leo B.
    Commented Sep 6, 2017 at 18:31
  • 1
    Since I have not yet found an architecture ref manual online (anyone?), I'm just noting that this J-11 manual lists differences in Appendix B.
    – dave
    Commented Sep 21, 2019 at 23:25
7

Instruction set differences

Retyped from DEC manual EK-PDP94-MG-001, PDP-11/94-E System User and Maintenance Guide, Appendix D.

Item 23/24 44 04 34 LSI11 05/10 15/20 35/40 45 70 60 J-11 T-11 VAX
JMP %R or JSR reg,%R traps to 10 X X X X X X X X X na
JMP %R or JSR reg,%R traps to 4 X X X X na
SWAB does not change V X
SWAB clears V X X X X X X X X X X X X
Register addresses (177700-177717) are valid program addresses when used by CPU X 1 1
Register addresses (177700-177717) time out when used by CPU; can be used by console X X X X X X X X na
Register addresses (177700-177717) time out when used by CPU or console X X X
Basic instructions noted in PDP-11 processor handbook X X X X X X X X X X X X X X
SOB, MARK, RTT, SXT instructions 2 X X X X X X X X X X 3
ASH, ASHC, MUL, DIV, XOR X X X X X X X X X 3
Floating Point instructions in base machine X X
MFPT instruction X X X
External KE11-A option provides MUL, DIV, shift operation in the same data format X X
KE11-E option (EIS) provides MUL, DIV, ASH, ASHC. These new instructions are 11/45-compatible X

Notes:
1. Register addresses (177700-177717) are handled as regular memory addresses in the I/O page.
2. RTT instruction is available in 11/04 but is different to other implementations.
3. All but MARK.

1
  • Nice. You found the list and even posted a formatted version. Thanks! For anyone not looking full screen -- the full width of table may not be showing. I had to expand my window. There is also a thin little scroll bar at the bottom of table which took me a while to notice.
    – RichF
    Commented Feb 4 at 4:23
3

The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples:

Inconsistent instructions

Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes,

From Bitsavers the PDP-11 Systems Handbook 1987, Appendix A-PDP-ll Family Differences Table states:

The table that follows illustrates the issues involved in software migration between different members of the PDP-ll family.

This table starts with base model processors from the PDP-11's line of second generation processors (e.g. PDP-11/05) through to the early VAX systems (e.g. VAX-11/7xx series). All these processors were microprogrammed implementations of the PDP-11 instruction set. Note: only the first generation PDP-11/20 was not microprogrammed and this processor is not included in this Appendix.

The table occupies 15 pages of the manual and is broken down into the following topics:

  • Instructions or Instruction Sets (5 Pages)
  • Memory Management and Relocation (2 Pages)
  • Interrupts (1 Page)
  • Buses (1 Page)
  • Processor Status Word (2 Pages)
  • General Purpose Registers (1 Page)
  • Error Handling (2 Pages)
  • Consoles and Serial Ports (1 Page)

Each member of the family has some small difference in the way it executes instructions.

The instruction set implemented on a particular site would be dependent on processor model number as well as the processor options fitted. There was: Base Set Extended Arithmetic Element (EAE) e.g. KE-11A Floating Instruction Set (FIS) e.g. KE11-F Floating-Point Processor (FPP) e.g. FP-11A Commercial Instruction Set (CIS) or Extended Instruction Set (EIS)

For the PDP-11 the memory bus could be 16, 18 or 22 bits wide therefore the amount of physical memory that an assembly language program could address varied significantly.

Therefore moving an assembly language program between systems could be a problem. If the assembly language program was limited to the Basic Instruction Set then the differences were small.

Therefore you might want to question the statement that there were only subtle differences when the differences were described by a 15 page table.

Any program developed using PDP-ll operating systems with higher level languages will migrate from one system to another with very little difficulty.

Missing instructions could be emulated by the systems so there was only a speed penalty. For the majority of high level applications migration could be accomplished with little difficulty.

though no implementation was regarded as correct.

The Appendix A simply stated that "each member of the family has some small differences in the way it execute instructions." No processor was identified as having the 'correct' version. Therefore no implementation was regarded as correct.

My semi-recollection/semi-guess is that the differences could be due to variations in micro-programs dealing with auto-increments or auto-decrements of registers when a memory access interrupt occurred.

Can anyone shed light on these "subtle differences"?

The Appendix A table identifies which systems incremented addresses by one or two./

The fact that no implementation was regarded as correct deserves another question: was there another instruction set architecture with similar inconsistencies without an officially declared correct way of implementing the architecture?

The answer to the stricken question is likely negative; as there is no way to prove a negative except by exhaustive research, and I wouldn't want to have a virtually unanswerable question under my name, I will not post it separately, unless someone would want to answer it positively.

There were a number of manufacturers that offered systems configured with writable microprogram storage. In the IBM 360/40 the additional microcode could add additional instructions that emulated the IBM 1400 series. The DEC VAX-11/750 had a writable User Control Store option that allowed custom instructions to be implemented

3
  • With respect to the question of whether the differences were 'subtle' or not: generally, DEC programmers knew what to stay away from. Looking at the appendix, I think the only one that was troubling was the "same source/dest register with autoinc/dev", but that was well-known. Missing instructions weren't a big deal, you'd just define macros and assemble specifically for the processor. (Also, my stuff never needed to run on pre-EIS CPUs).
    – dave
    Commented Jan 6, 2022 at 1:21
  • As the question concerns specifically "implementation of instructions and combinations of addressing modes", the relevant differences occupy only 5 pages., maybe 6 if interrupt handling may vary due to addressing modes. Is 5-6 pages subtle enough for you?
    – Leo B.
    Commented Jan 6, 2022 at 9:08
  • High level language applications were not impacted. Most people would not have cared. Cost, performance, storage and communications would have been the focus of attention. Even a description of 'subtle' is overstating these differences. Only a limited subset of programmers working with one of the assembler implementations (e.g. PTS) would have known. I've had to single step microcode, and hand assembled programs to run in register memory, etc., and never was concerned. I attempted to provide a reference to appropriate, source material. Decision of level of sublety I can leave to others.
    – PDP11
    Commented Apr 20, 2022 at 8:34

You must log in to answer this question.

Not the answer you're looking for? Browse other questions tagged .