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The wiki page PDP-11 architecture has a cryptic paragraph with no references or examples:

Inconsistent instructions

Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes, though no implementation was regarded as correct. The inconsistencies did not affect ordinary use of the PDP-11.

My semi-recollection/semi-guess is that the differences could be due to variations in micro-programs dealing with auto-increments or auto-decrements of registers when a memory access interrupt occurred.

Can anyone shed light on these "subtle differences"?

The fact that no implementation was regarded as correct deserves another question: was there another instruction set architecture with similar inconsistencies without an officially declared correct way of implementing the architecture?

The answer to the stricken question is likely negative; as there is no way to prove a negative except by exhaustive research, and I wouldn't want to have a virtually unanswerable question under my name, I will not post it separately, unless someone would want to answer it positively.

A contemporary example would be a difference between Intel and AMD in their handling of a jump instruction with a data size override prefix (punchline at 32m50s).

  • I would suggest posting your second question as a second question. – a CVn Sep 6 '17 at 6:22
  • @MichaelKjörling It will make sense splitting them as soon there is a concrete example of what exactly it asks about (cf. "similar inconsistencies") in the form of an answer to the first question. – Leo B. Sep 6 '17 at 7:18
  • THe only 'inconsitency' I can think of are extensions (like FP, etc) that have been only available on certein machines - and unlike the PC development, not enhanced machiens where sold for decades after. Same goes for certein instructions and their behaviour on muti processor memory, depending on the momory implementation. But thats (mostly) restricted to I/O access. – Raffzahn Sep 6 '17 at 7:59
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Here is an example:

mov r5,-(r5)

That moves the contents of R5 to the address location specified in R5 after first decrementing R5. The question is what gets put in the memory location? Is it the contents of R5 before the instruction was started or is it the decremented R5.

For example, if R5 contained 10 (decimal), usually the microcoded PDP-11s, would put 10 in location 9. Others, the earlier non microcoded ones, would put 9 in location 9.


Source: The book PDP-11 Architecture Handbook, 1983, digital, verifies this in Appendix B, "PDP-11 Family Differences". Specifically, the models 23/24, 15/20, 25/40, 60, J-11, and T-11 would pre-decrement r before using it. The 44, 04, 34, LSI-11, 05/10, 45, 70, and VAX would not.

  • Interesting, makes sense. Is there a chance you could add some source for further reading? – Raffzahn Sep 6 '17 at 8:57
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    That example comes from github.com/gaojiechina/os_collection/wiki/PDP-11-architecture – JeremyP Sep 6 '17 at 9:00
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    Now that's interesting. The page you linked is a verbatim copy of the Wiki artikle about the PDP architecture from 2014 - but exactly that paragraph got removed in 29015, as 'just guesses' and quite frankly, a change that important would break many programms, while the paragraph before mentioned that 'normal programs are not affected'. See here en.wikipedia.org/w/… – Raffzahn Sep 6 '17 at 9:10
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    Would be great if there are any, as this one seams to be not verified. I just went thru the manuals for the PDP11/20 (KA11 non microprogram) and 11/45 (KB11 microprogrammed) and couldn't find any hint. Same on the 1975 programming card. One would expect to find some when the difference is that obvious. – Raffzahn Sep 6 '17 at 10:02
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    The book PDP-11 Architecture Handbook, 1983, digital, verifies this in Appendix B, "PDP-11 Family Differences". Specifically, the models 23/24, 15/20, 25/40, 60, J-11, and T-11 would pre-decrement r before using it. The 44, 04, 34, LS1/11, 05/10, 45, 70, and VAX would not. – RichF Sep 6 '17 at 14:01
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As I remember, there were the following inconsistensies:

  • Jumping to an odd address could bring different results (trap or continuing from the closest even address)

  • Byte operations with the stack pointer. In some models this would be working as with any other register, decrementing/incrementing SP by one, in others only increment/decrement of SP by 2 was possible.

  • Byte move to a registry on some models would fill the other byte of the registry with sign.

  • Different behavior of some SWAB and bit mask operations, I do not remember details.

5

Some PDP-11 family computers could address its own registers as the top 8 (16-bit) addresses in its address space. (The top 4 kwords were sometimes dedicated to an I/O page.) For example, a program running on the 05/10 model could place a short loop in R2 to R5 and execute it from those registers. On most models, however, accessing those locations would yield a time-out.

The above is item 7 in a 52-member list of architecture instructional differences within the PDP-11 family, as itemized in Appendix B, "PDP-11 Family Differences" of_PDP-11 Architecture Handbook, 1983, digital. Most are quite minor or obvious, such as some PDP-11s had the Extended Instruction Set (EIS) or floating point and some did not.

  • Differences of the kind "a program works on one platform and causes a bus error or an illegal instruction exception on another" are anything but subtle. Are there other items in the list similar to the one above? – Leo B. Sep 6 '17 at 15:46
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    @LeoB. Yes. For example the 4th listed variance is the behavior of JMP (R)+ (as well as JSR (R)+). On some models the register would be incremented by two first, whereas other models would immediately jump to the given value of R. I checked to see if I could find a copy of this book online, but I could not find it. – RichF Sep 6 '17 at 16:36
  • I see. Then, apparently, the self-propagating instruction 014747 MOV -(PC), -(PC) would have worked on some platforms but not others? – Leo B. Sep 6 '17 at 17:41
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    FWIW, MACRO-11 would flag the instructions that are known to cause different behaviour (error code Z), see MACRO-11 Lang Ref Manual. – sendmoreinfo Sep 6 '17 at 17:47
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    @RichF You may want to move your comment about JMP (R)+ to the answer. – Leo B. Sep 6 '17 at 18:31

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