I am trying to understand the Amiga schematics:

Question 1: What is the necessity of the Signal BLS (Blitter SLow) generated by A2000A U26 or Gary in the A2000B?

Question 2: BLS is also set by access $C0-DFFFFF. (SlowRAM, RTC and ChipRegister) Is there an Interaction with the Blitter too?

  • BLS is also set by access $C0-DFFFFF. (SlowRAM, RTC and ChipRegister) Is there an Interaction with the Blitter too? – Gonzo Dec 17 '17 at 21:10
  • I'm almost inclined to as if you ever looked at the schematics :)) Lets move that up and do a combined answer. – Raffzahn Dec 17 '17 at 23:14

It's BLitter Slowdown and an input signal to Agnus, telling the DMA logic to free a cycle for the CPU if possible - a situation which normaly arises during Blitter operations, thus the name.

From Amiga System Programmers Guide (English language version of Data Becker's Amiga Intern) p.29:

The BLS signal (BLitter Slow down) signals Agnus that the processor has already waited three bus cycles for an access. Depending on its internal state, Agnus turns the bus over to the processor for one cycle.

(AFAIR there was somewhere a configuration bit for Agnus, called 'Blitter Nasty' which, when set tells the DMA to ignore BLS. So it's not always working :)


And yes, there is a good and quite simple reason for BLS being active for access to the so called 'Slow-RAM' (or Ranger-Memory): It's managed by Agnus and thus technicaly Chip-RAM. So while the ECS/Fat-Agnus could handle more memory (addressing & refresh), the video related registers didn't get extended, thus the additional memory could not be used the same way as the original Chip-RAM.

Next question could be why at all, and as usual with Commodore it's all about money, even after Tramiels demise. Adding the ability to address and refresh more memory as a partitial redesign of the Agnus enabled the production of dirt cheap memory expansions for the A500. No need to add refresh logic, complex address decoding or whatsoever, just nail the RAMs onto the bus and sell them fast and in masses.

Why at that location? Well, for one, they didn't want to give up the chance to use the full 2 MiB range reserved for Chip-RAM (up to 1FFFFF), but more important, that area was already decoded by the Agnus anyway. So C00000ff it was. This is also the reason why there are memory expansions for the A500 with up to almost 2 MiB (~1,75 or so) Ranger Memory possible (with a little Garry hack). They utilize the whole C/Dxxxxx range except the registers. Still ofc with the Chip-RAM brakes set.

  • How much control is there? I would think that in cases where both the CPU and blitter have some work to do, it would make sense to have the blitter run only during idle cycles as long as the CPU is doing useful work, and then have the CPU idle (so it would no longer impede the blitter) until the next interrupt. Can the blitter do that, or must it always grab more cycles any time it's active? – supercat Dec 17 '17 at 18:51
  • 1
    That's the whole reason for this setup - including the nasty bit. For one, they only compete for the bus when the CPU is accessing the Chip-RAM. Next, the blitter is higher priorized, since it's access (well, all DMA in fact) is usually real time dependant. So by default the blitter gets 75% of RAM time, the CPU 25%, which translates to braking the CPU only less than 30%. So both can work mostly in parallel. And with 'Nasty' it gets all cycles. Remember, whatever the blitter does is (usually) visible, and noone wants jittering screen updates. As usual YMMV – Raffzahn Dec 17 '17 at 19:38

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