The SC/MP seems to have been designed right from the start with a 12 bit address bus and 4 additional "page" bits. To quote from p. 1-4 of the SC/MP Technical Description:
The SC/MP chip has a 16-bit address capability; thus, any
one of 65,536 memory locations can be discretely specified. As shown in figure 1-4, four of the address bits are
sent over the data bus to select-any of 16 memory "pages,"
and 12 bits are sent over the address bus to specify the
memory location within the page. ROM, PROM, and RAM
memories may be intermixed in the address space.
So not only are the upper 4 bits not incremented, they are also sent over the data bus early in the bus cycle and need to be latched to be useful. Which means many simpler systems would have used only 12 address bits, anyway.
The paging/banking technique is nothing unusual, it was quite commonly used in many computers from minis to home computers to extend the address range.
As to why it was done this way, one can only speculate:
- Possibly the SC/MP was originally designed with a 12 bit address bus, and the additional 4 address bits are an afterthought and were put in after most of the design was already done.
- As the SC/MP was intended as a microcontroller, possibly the designers saw an advantage to having a banked address range for handling interrupts etc.
- Possibly the adder in the ALU used is only 4 bits wide, and using the full 16 bit address range would have added another microcycle to the already large number of microcycles needed for each instruction, and that was considered to expensive.
I couldn't find any information about the width of the adder in the Technical Description, but the
ADI instruction needs one more microcycle than the
XRI instructions, which is exactly what would happen if and/or/xor were 8-bit wide, but add only 4-bit wide.
To actually verify this theory, one would need to decap a chip, and reverse engineer the silicon. This has been done for other chips, e.g. the 6502, but to my knowledge not for the SC/MP.
More hints that the adder is possibly only 4 bits wide:
DLY operation takes
13 + 2 * (AC + disp + 2^8 * disp) microcycles, which is exactly what you'd get counting down AC and another internal register, if each decrement would need 2 microcycles. Though it could be of course an 8-bit decrement in one cycle, and one cycle to check for zero, but that would be really wasteful.
Bus accesses are 2 microcycles wide, and it takes 4 bus cycles from the opcode byte read until the bus read for the operand byte. That would be necessary if 3 cycles are needed to increment the 12-bit address in the PC (and 1 cycle for something else, e.g. instruction decode). Again, there are alternatives: if 2 cycles are needed for an 8-bit add and a 4-bit add, the other 2 cycles might be needed for something else.
The Z80 also uses a 4-bit ALU.