The SC/MP (the processor found in the MK14) had four 16-bit address registers (and one of these was also the program counter).

If you add something to these registers, or increment these registers, the topmost 4 bits will not change. To change those top 4 bits, your program needs to set them separately.

My question is why were the pointer registers designed to work in this way? Did they save some gates, not expecting to see huge (for the time) 64 KiB of memory? Or was it to better support coroutines somehow? Or were they expecting users to have metadata in that part of the pointer, as the Macintosh Classic did?


The SC/MP seems to have been designed right from the start with a 12 bit address bus and 4 additional "page" bits. To quote from p. 1-4 of the SC/MP Technical Description:

The SC/MP chip has a 16-bit address capability; thus, any one of 65,536 memory locations can be discretely specified. As shown in figure 1-4, four of the address bits are sent over the data bus to select-any of 16 memory "pages," and 12 bits are sent over the address bus to specify the memory location within the page. ROM, PROM, and RAM memories may be intermixed in the address space.

So not only are the upper 4 bits not incremented, they are also sent over the data bus early in the bus cycle and need to be latched to be useful. Which means many simpler systems would have used only 12 address bits, anyway.

The paging/banking technique is nothing unusual, it was quite commonly used in many computers from minis to home computers to extend the address range.

As to why it was done this way, one can only speculate:

  • Possibly the SC/MP was originally designed with a 12 bit address bus, and the additional 4 address bits are an afterthought and were put in after most of the design was already done.
  • As the SC/MP was intended as a microcontroller, possibly the designers saw an advantage to having a banked address range for handling interrupts etc.
  • Possibly the adder in the ALU used is only 4 bits wide, and using the full 16 bit address range would have added another microcycle to the already large number of microcycles needed for each instruction, and that was considered to expensive.

I couldn't find any information about the width of the adder in the Technical Description, but the ADI instruction needs one more microcycle than the ANI, ORI and XRI instructions, which is exactly what would happen if and/or/xor were 8-bit wide, but add only 4-bit wide.

To actually verify this theory, one would need to decap a chip, and reverse engineer the silicon. This has been done for other chips, e.g. the 6502, but to my knowledge not for the SC/MP.


More hints that the adder is possibly only 4 bits wide:

  • The DLY operation takes 13 + 2 * (AC + disp + 2^8 * disp) microcycles, which is exactly what you'd get counting down AC and another internal register, if each decrement would need 2 microcycles. Though it could be of course an 8-bit decrement in one cycle, and one cycle to check for zero, but that would be really wasteful.

  • Bus accesses are 2 microcycles wide, and it takes 4 bus cycles from the opcode byte read until the bus read for the operand byte. That would be necessary if 3 cycles are needed to increment the 12-bit address in the PC (and 1 cycle for something else, e.g. instruction decode). Again, there are alternatives: if 2 cycles are needed for an 8-bit add and a 4-bit add, the other 2 cycles might be needed for something else.

The Z80 also uses a 4-bit ALU.

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    The most common reason to only use some bits of the available address range is to reduce pin count. (It's why current 64-bit CPUs only really use 48 address bits right now.) – Mark Dec 21 '17 at 21:13
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    Even if the ALU is 8 bits wide, when addresses are generated it may well take an extra cycle for carry to propogate from bit 0 all the way to bit 12, and as the top four bits are needed in the cycle before the rest of the address, the designers may have found that they couldn't have the complete address available without delaying address generation a cycle. They may therefore have decided to simply not apply carry operations forwards to the upper 4 bits so that this wasted cycle isn't needed. – Jules Dec 21 '17 at 22:18
  • @Mark: But reducing pin count doesn't mean you are forced to use a paging/banking scheme. Multiplexed data/address busses on CPUs without such a scheme are quite common ... – dirkt Dec 21 '17 at 22:44
  • Maybe even a "4096 bytes is just about enough for everyone"-thing. – tofro Dec 22 '17 at 9:35

The SC/MP didn't really have a 16-bit address bus - It rather had a 12-bit adddress bus and four additional latchable lines that could serve as the upper 4 bits of a 16-bit address bus. This is also reflected in the inner register structure and clearly pointed out in the data sheet.

The data sheet also mentions

To conserve pinouts on the chip, the absolute-addressing capability of the pointer register is subdivided

Which explains they limited the external addressing capability of the chip to 4k to be able to fit the CPU in 40-pin DIP. I would expect that the limited register width saving some valuable chip space was a welcome side effect.

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