According to https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM

Page mode DRAM is a minor modification to the first-generation DRAM IC interface which improved the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column.

Minor in implementation difficulty, but major in performance implication; faster multiword data transfer can substantially speed up many operations.

When did CPUs start being able to make use of this? The instruction timing tables I've seen for seventies and early eighties CPUs such as the 6502, Z80 and 68000 suggest they did not use page mode. On the other hand, I've found a few PDFs that indicate the 68030 did. I haven't been able to find anything definite on the 68020. (Apparently the video chip on the Sinclair Spectrum did use it, so even if the CPU didn't, the capability didn't go to waste.)

3 Answers 3


Outside of the world of microprocessors, there were plenty of CPUs that did this. Up until some point in the mid 80s, TTL-based multichip CPUs were generally faster than microprocessors and therefore the memory interface was often the bottleneck for such systems. The Xerox Alto, for example, had a processor that could theoretically run at a rate much faster than it actually did; it was slowed down to 5.88MHz because that was the fastest its RAM could supply instructions and data to it. I don't have an unambiguous indication that it uses page mode, but as the RAM bank uses 4116-2DC chips which are 150ns type chips (and therefore have a page mode cycle time of 170ns == 5.88MHz vs a full cycle time of 375ns == 2.67MHz) it seems pretty clear that the Alto was using them in page mode.

The Alto also used them arranged in 16-bit words, so the Alto's processor meets the requirements of the additional question you asked in the comments to Raffzahn's answer: it is apparently able to read a 16-bit word in a single cycle at 5.88MHz, which appears to be the rate at which its microcode was processed -- it used programmable microcode, so how user-level instructions were handled could vary depending on the software it was running.

For microprocessors, it was less necessary, because most of the well known ones were nowhere near this fast -- I suspect the 80286 was the first mainstream microprocessor that could actually use memory quickly enough to require it: running at 8MHz (the 10MHz and 12.5MHz variants were released later) it requires a memory access response time of 138.5ns to operate with zero wait states, and may perform another access one cycle later (i.e. 250ns after the initial access began). While by the time of its release in 1982 there were faster DRAM chips available that could have managed that, they were very expensive, so I imagine most implementations of 8MHz 80286 machines used page mode, at least for the first few years after the 286 was launched (although I'm pretty sure that by the time my 286-based PC was made in 1987 that at least some manufacturers were simplifying their systems by using the faster RAM that was becoming cheaper by then).

That said, even in micro systems, there were cases where you may have needed the extra performance you could get from using page mode, because the CPU isn't the only component of the system that needs to use memory. As mentioned, the ZX Spectrum uses page mode to fetch 16 pixels worth of information in the tight window that exists between possible successive uses of the bus by its CPU. It wouldn't have enough time to get them in a single gap otherwise, and only getting 8 pixels per gap would leave it taking too long to generate each scan line. More advanced graphical systems than the spectrum's could easily have tipped the balance into needing to use page mode for CPU accesses in order to steal enough bus time to produce a line. Other uses might include DMA for disk-based systems, coprocessors, blitters, or other similar alternative memory users.

A system I'm planning on building at some point would have two pluggable CPU boards (I'm planning on having both a Z80B and a second board that lets any CPU I want to experiment with be plugged into the shared bus) and a graphics system sharing access to a single 16-bit wide memory space. I'm hoping that by caching bytes adjacent to the last access locally to the CPU and using page mode where possible, all three of these users should be able to hit memory whenever they want with very little waiting. It'll be interesting to see if it works out that way...

  • The Question is not (primarily) abbout speed, but memory handling. The main missunderstanding many have is that a CPU has to have an understanding of internal workings of memory. But that's not the case. A CPU sets out a memory request, and the memory delivers. With the exception of simple (static) RAM this will happen in various timing. To handle this, the memory subsystem communicates with the CPU request. On a 68k for example by assering DTACK when ready. So not the CPU is responsible but the memory controler to integrate things like page mode. Its system speed vs. CPU speed.
    – Raffzahn
    Commented Dec 30, 2017 at 12:24
  • 8088 (and somewhat 8086) were notoriously bottlenecked by memory access. See for example When specifying Intel 80x86 instruction execution time, what is included in the cycle count? and Increasing Efficiency of binary -> gray code for 8086 . Was that not limited by the actual speed of DRAM, but actually how many cycles the bus-interface-unit took to get a memory access done? Or would page-mode have been a speedup for 8086? CPUs without cache will tend to have good spatial locality for code-fetch at least Commented Mar 28, 2023 at 4:12

DRAM access in general and page mode (*1) in particular are not CPU features, but depend on the DRAM controller. No matter if build by discrete components (like mulitiplexers and counters) or dedicated IC. Pagemode DRAM can be used with any CPU if the controller (access logic) used supports its features. No matter if it's an 8080 or a 68020.

You won't find any CPU related information on such RAM access techniques until the point in time where memory controllers got integrated into CPUs. For x86 this might be the AMD K8 or Intel's Core-i7. All PC CPUs before did use separate memory controllers. Originally discrete logic, which slowly got moved into what later was known as 'Northbridge'. Beside x86, IBMs Power 5 and the Cell series got also integrated memory controllers around the same time.

So all the time between introduction of PM/FPM/EDO from ~1977(?) till ~2005, it was used without any CPU having an idea about its workings. Wasn't having separate technology domains a great idea?

  • 1
    As you say, fast page mode depends on the memory controller, which until relatively recently was a separate chip, but I would have thought it also depended on the CPU? A 68000, for example, is specified to take 4 clock cycles per word. Presumably a fast page mode memory controller might read a double word in e.g. 6 cycles, but that won't help if the CPU doesn't know about this, and ends up waiting the full 8 cycles anyway?
    – rwallace
    Commented Dec 28, 2017 at 2:07
  • 1
    Since when is a CPU clock in any way related to the internal workings of a RAM? A CPU puts out an address and waits for data. at the end of the cycle (or longer if some wait sate is triggered). It doesn't care how the RAM is accessed. It's the job of the designer of the DRAM access controller to create a circuitryy to link them up. And how it's done isn't necersarry speed.
    – Raffzahn
    Commented Dec 28, 2017 at 2:11
  • 2
    @rwallace A 68k CPU will not wait for a specified time until memory becomes valid - It will wait for a DTACK signal that tells it data bus signals are valid, i.e a memory controller.
    – tofro
    Commented Dec 28, 2017 at 2:17
  • @tofro And then there was DTACK Grounded :)) SCNR
    – Raffzahn
    Commented Dec 28, 2017 at 2:23
  • Okay, concrete requirement: make a 68000 (or similar chip with a 16-bit data bus) read a double word in fewer than 8 clock cycles.
    – rwallace
    Commented Dec 28, 2017 at 2:29

A number of British 8-bit home computers built around Ferranti ULAs used page mode in some way. The timings for DRAM are tricky. If you look at the timings they aren't nice multiples. Even with, say, a 16 MHz crystal there's going to be cludges.

  • Sinclair Spectrum - As mentioned by OP. There is a byte of attribute data (RGB foreground, background, intensity bit and flash) per 8x8 bit-mapped character cell. The ZX Spectrum Ula: How to Design a Microcomputer book goes into some detail about how the memory is arranged such that these nine bytes end up in the same DRAM row, and then a few pages later shows a diagram with the wrong timings. This prevents too much conflict with the Z80, particularly the 16K Spectrum.
  • Amstrad (non-Sinclair) 8-bits (apparently including 8256, which uses a big CPLD) - These have a normal bit-mapped frame buffer. Two bytes are read in pairs between each CPU access. It seems the effect of this is to keep the Z80 M-cycles to be effectively a multiple of four T-cycles (i.e. clock cycles). M-cycles would usually be 3 or 4 cycles. Hence sometimes you'll see the clock speed quoted with an odd number - it's 4 MHz with a few skipped.
  • Acorn Electron. (In most machines the hot Ferranti ULA with very high failure rate is replaced by a VLSI Technology CMOS ASIC.) A 32K machine using only 4164 (space for a 4464 alternative), means that the DRAM data bus is only 4 bits wide! Whilst with 230 ns that could be accessed at 4 MBps, timing makes it easier to use page mode to access both nibbles of every byte. The 6502 really bashes the bus - every cycle, as there is it provides no way to share. So Z80-style tricks wont work.
  • Oric-1/Atmos - Probably does something similar. It has very odd 6x8 block+attribute modes.

It's strange that it wasn't used more extensively. Take the 90's Acorn A3010/A3020/A4000 series computers. With modern RAM you can "overclock" them to twice their original speed. With the DRAM (+video and I/O) controller integrated, page mode would have been an easy win.

  • The MEMC1 in the Acorn 32 bit machines required fast page mode DRAM - ARM1 through ARM3 use the SEQ signal to tell MEMC that they're doing a sequential access, and MEMC controls the CPU bus timings so can either let them do a fast page mode access, or a slower access, at its discretion. Commented Mar 28, 2023 at 18:01

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