Outside of the world of microprocessors, there were plenty of CPUs that did this. Up until some point in the mid 80s, TTL-based multichip CPUs were generally faster than microprocessors and therefore the memory interface was often the bottleneck for such systems. The Xerox Alto, for example, had a processor that could theoretically run at a rate much faster than it actually did; it was slowed down to 5.88MHz because that was the fastest its RAM could supply instructions and data to it. I don't have an unambiguous indication that it uses page mode, but as the RAM bank uses 4116-2DC chips which are 150ns type chips (and therefore have a page mode cycle time of 170ns == 5.88MHz vs a full cycle time of 375ns == 2.67MHz) it seems pretty clear that the Alto was using them in page mode.
The Alto also used them arranged in 16-bit words, so the Alto's processor meets the requirements of the additional question you asked in the comments to Raffzahn's answer: it is apparently able to read a 16-bit word in a single cycle at 5.88MHz, which appears to be the rate at which its microcode was processed -- it used programmable microcode, so how user-level instructions were handled could vary depending on the software it was running.
For microprocessors, it was less necessary, because most of the well known ones were nowhere near this fast -- I suspect the 80286 was the first mainstream microprocessor that could actually use memory quickly enough to require it: running at 8MHz (the 10MHz and 12.5MHz variants were released later) it requires a memory access response time of 138.5ns to operate with zero wait states, and may perform another access one cycle later (i.e. 250ns after the initial access began). While by the time of its release in 1982 there were faster DRAM chips available that could have managed that, they were very expensive, so I imagine most implementations of 8MHz 80286 machines used page mode, at least for the first few years after the 286 was launched (although I'm pretty sure that by the time my 286-based PC was made in 1987 that at least some manufacturers were simplifying their systems by using the faster RAM that was becoming cheaper by then).
That said, even in micro systems, there were cases where you may have needed the extra performance you could get from using page mode, because the CPU isn't the only component of the system that needs to use memory. As mentioned, the ZX Spectrum uses page mode to fetch 16 pixels worth of information in the tight window that exists between possible successive uses of the bus by its CPU. It wouldn't have enough time to get them in a single gap otherwise, and only getting 8 pixels per gap would leave it taking too long to generate each scan line. More advanced graphical systems than the spectrum's could easily have tipped the balance into needing to use page mode for CPU accesses in order to steal enough bus time to produce a line. Other uses might include DMA for disk-based systems, coprocessors, blitters, or other similar alternative memory users.
A system I'm planning on building at some point would have two pluggable CPU boards (I'm planning on having both a Z80B and a second board that lets any CPU I want to experiment with be plugged into the shared bus) and a graphics system sharing access to a single 16-bit wide memory space. I'm hoping that by caching bytes adjacent to the last access locally to the CPU and using page mode where possible, all three of these users should be able to hit memory whenever they want with very little waiting. It'll be interesting to see if it works out that way...