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The SAM Coupé was a ZX Spectrum compatible computer with a 6MHz Z80, 256K RAM minimum, enhanced graphics and sound and an improved BASIC amongst other features. My question is about its memory. The RAM in a standard SAM is two 44256 DRAM chips of 256Kx4 bits in a 512x512 row/column arrangement, so using 9-bit row/column addresses. The Z80 only has a 7-bit refresh counter and the SAM's display (in modes 3 and 4) can be completely switched off, giving the Z80 apparently uncontended access. So what refreshes all the memory rows? (Schematic reference: http://velesoft.speccy.cz/samcoupe_schematics-cz.htm )

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    Note video RAM contention is always there when CPU and video controller try to access the memory at the same time. It's especially bad on the Spectrum, because the CPU is even halted when it doesn't even try to access video memory (or any memory at all). That is the main improvement the SAM had over the Spectrum. – tofro Dec 29 '17 at 11:24
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    Well, since the memory addressing (CPU Address Bank) is generated and multiplexed in the ASIC, I guess it also contains a 9-bit refresh counter/logic - everything else wouldn't make sense. – Raffzahn Dec 29 '17 at 11:43
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    I'm not sure I'd call the Sam's memory contention an improvement over the Spectrum's: while the display is on, all memory is contended. There's no split bus, nowhere you can put your code to run at full processing speed (well, other than in ROM or in one of the 1mb RAM expansions, but nobody had those). That's enough of a detriment to outweigh any other benefit. – Tommy Dec 29 '17 at 13:19
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    @Tommy Right - It's an improvement with respect to looking at /MREQ before halting the CPU, but even worse in that there's no uncontended memory at all on the SAM. But that's probably the cost of being able to put screen memory into arbitrary places. – tofro Dec 29 '17 at 13:32
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    Well, in theory, 44256 chips support 'hidden' and 'cas-before-ras' refresh modes. They both generate refresh addresses internally in the chip, so Z80 refresh address is no more required. – lvd Jan 1 '18 at 8:45
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According to the schematic posted, the only possible component that could be performing the refresh is the chip identified as "ASIC". It has 9 pins labelled "MADD0".."MADD8", which are the only connections to the RAM address pins. I know that some work has been done reverse engineering this chip and maybe @mcleod_ideafix will let us know in more detail later, but I'm going to guess that it detects the Z80's refresh cycles and extends the refresh counter with a couple of extra bits. At 6MHz, this would generate a full cycle of refreshes in at most 2ms, so is clearly fast enough for the RAM, which requires all 512 rows refreshing in 8ms.

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