I am currently designing a watered-down version of the 6502 in Logisim. I am working off of Hanson's Block Diagram to build my subset. I have fully built the processor using the diagram and other resources as a reference in logisim, with the one exception being that I have combined the Random Control Logic And decode ROM into a single "Instruction ROM", seen below. Note that INF is the rest of the processor as a sub-circuit and the RAM is not fully wired yet.

System block diagram

I am at the the point of programming the control lines, and I am wondering if there is a place where I can find each opcode and the control lines sent out for each cycle of the clock. Is there a website or book that shows how each opcode is processed internally using either Hanson's terms or otherwise?

  • 1
    Have you ever finished your project? I'm also implementing a CPU from scratch in Logisim, but trying to learn from others' designs each step of the way. Aug 4, 2019 at 21:01
  • I "finished" the wired portion of the CPU but never quite got to programming the ROM chips. I can email you the project (logisim files and excel of where I got with the ROM programming) if you PM me.
    – Clink123
    Aug 6, 2019 at 3:12
  • There's no way to PM you, but I've created a chat here: chat.stackexchange.com/rooms/97125/retro-computing-6502 Aug 7, 2019 at 0:15
  • Cant talk until you let me in that group chat.
    – Clink123
    Aug 9, 2019 at 10:59

2 Answers 2


Visual6502.org has all you need: A table of the decode ROM, explanation of the control lines in the wiki and additional comments to control line names in the source.

(It's difficult to answer this question except by linking, I don't think a cut-and-paste copy of the ROM table makes sense here).

  • Keep in mind, the List you liked is for the Atari 6507 and does show a few differences to the 6502 as simulated by Visual6502.
    – Raffzahn
    Jan 13, 2018 at 19:00
  • @Raffzahn: I would expect that the 6507 would use the same die as the 6502, but with only 28 of the bonding pads connected to pins on the package. Is there any other physical difference?
    – supercat
    Jan 15, 2018 at 18:13
  • I've been told that there are differences between the 6507 schematics and what the Visual6502 project discovered. After all, the 6502 has not been produced all the years from the same masks.
    – Raffzahn
    Jan 15, 2018 at 18:24
  • @supercat: the different original NMOS 650x members do have slightly different dice for the clock generator (6501 vs 6502..6507 vs 651x) and for any unused inputs (on-chip pullups). The difference is probably only the metalization layer, though I haven't verified that.
    – Eric Smith
    Nov 21, 2018 at 19:58
  • @EricSmith: From what I've read, even the processor in the Nintendo Entertainment System, which is deliberately designed not to support decimal mode in compatible fashion, uses the same layout as the 6502. I guess if there was no reason to change things, there was no reason to change things. I'll admit that I find it odd that chips like the 6510 weren't designed to exploit unused opcode spots. Adding circuitry so that a fetching certain byte values with SYNC active would substitute an opcode that behaves as a no-op while setting or clearing an output latch would seem just as easy...
    – supercat
    Nov 21, 2018 at 20:32

Is there a website or book that shows how each opcode is processed internally using either Hanson's terms or otherwise?

No. At least none I've come across while researching the 6502. For most parts, the Decode ROM already provides the needed insight. After all, most instructions follow the same flow, usually defiened by the way memory access is done.

I guess, when thinking about, everyone realizes that it's that simple. No explicit intermediate step is needed. Not to mention, these combinations are the reason this part has not been made up as regular ROM. It's way more efficient that way.

By drawing up some simple sheets for each basic instruction flow, you'll easy see what groups of signals are needed to be activated. The Decode ROM, as well as an Opcode Matrix, will be useful. That's at least the way I went.

Further, Visual 6502 is a great help. Here especially the handy simulator. Here it's rather easy to follow each signal and see the workings.

Keep in mind that Hanson's diagram does leave out some important signals and loopbacks, as it's meant to underline specific points in his articles, not documenting the whole design. It's neither complete nor conflict free.

The 6507 sheets, and Beregnyei Balaz's rather complete transistor level drawings, are more revealing but of course a lot harder to read than a high level block diagram.

P.S.: It might be interesting to see how you managed the integration of the so called 'Decode ROM' and 'Random Logic' into a single classic(?) ROM

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    I haven't used Logisim, but I suspect it can handle a ROM of arbitrary size. The 6502's decode ROM & random logic are AFAICT purely combinatorial, so they can be implemented as a traditional ROM, although it would be somewhat larger than the original implementation. They used a lot of tricks to keep the size small (e.g. only partially decoding the addresses coming in), but for simulating it on a modern computer that's really not necessary...
    – Jules
    Jan 12, 2018 at 15:52
  • @Jules right. It's mostly combinatorial, but it also got a hand full of flipflops, which would make a simple ROM rather wide. So no doubt it can be done ... like most things on earth could. Still, the way it is done is something I like to see.
    – Raffzahn
    Jan 12, 2018 at 15:58
  • The way that I accomplished this was by creating an addressing ROM with the instructions at their original hex locations and then using that to call a location in my very large instruction ROM. The Instruction ROM is very large (which is why there are two, as I exceeded logisim's limit) but for each memory address accessed, there are 48 control lines output to the rest of the processor. Take a look at the spreadsheet I'm using to (try to) organize this here: Spreadsheet for Opcodes
    – Clink123
    Jan 13, 2018 at 15:59
  • I'd love to see how this mechanic should handle for example a page overflow cars on some instruction with indexed adressing.
    – Raffzahn
    Jan 13, 2018 at 19:12

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