A ZX Spectrum is likely to lose the same bit of every memory address if a single DRAM chip fails completely.

However, if a DRAM chip partially fails, this could cause... interesting issues, especially when coupled with such an unusual architecture as in the ZX Spectrum (which I suspect might be more common than I know).

  • In what ways would DRAM fail? (e.g. bad reads, bad writes, translated reads / writes, address line failure)
  • What software-visible patterns would appear in the memory behaviour? (e.g. garbage data, missing data, moving data, duplicated data)

I will accept both errors caused by natural component deterioration and by sufficiently advanced incompetence.

  • This paper looks promising (DOI: 10.1109/SC.2012.13) but I don't have access to it at the moment. (Also, it's referencing stuff like Rowhammer which wasn't as much of an issue with earlier DRAM chips, so I don't know how relevant it is.)
    – wizzwizz4
    Jan 13, 2018 at 21:14

1 Answer 1


The ZX Spectrum memory isn't a particularly "unusual architecture" as these things go, and you will see much the same faults as on other platforms:

  • A solder bridge or chip fault which ties an address line to 0, 1, or to another address line or other signal. This will manifest itself as aliased memory locations. A simple memory test of the kind often used to determine the size of memory will not detect this.

  • The same kind of fault which affects a data line. The Spectrum has one data line per chip which makes it marginally harder to debug, and is normally just assumed to be a bad chip rather than a build fault. This will look like a stuck bit across the whole chip and is really obvious to any tester that's not total gash. A machine won't boot in this state unless the RAM is some additional bank (on the Spectrum, anything beyond 16kiB) which is not used by the boot process.

  • The same fault again affecting the address decoder (e.g. a 74138 3-to-8 decoder). In this case, multiple chips might be enabled for writes, or not enabled when they are supposed to, so accesses will go to the wrong memory location, or multiple locations, or none. If it's "only" a partial or design fault, this can be infuriating to detect because the circumstances causing the bad decode might be very rare. The infamous "dead cockroach" fix in early ZX Spectrums is a fix for this class of problem. A simple memory tester that writes then immediately reads may not detect this either, as the value never actually enters memory but hangs around in the stray capacitance on the bus.

  • A bad memory cell within the chip. A cell is a transistor and a capacitor which are both ultimately analogue devices. When the device is working and being used correctly, they will ensure that the capacitor stably holds the value that was previously written. On total failure, the bit will stick to one value; on partial failure the cell will be weak and intermittently flip. Worse, the partial failure tends to be temperature-related, so the machine might need to warm up before it works properly, or it stops working after it's warmed up. A badly-designed or faulty refresh circuit may also run DRAM out-of-spec and cause this sort of problem.

As you might guess, testing memory is a harder problem than it initially appears. It is only possible to prove that memory is bad, and impossible to prove that it is good. Fortunately, if you perform a thorough-enough test for bad memory and find nothing, it is safe enough to assume it works.

  • Thanks for this answer. I don't quite understand "as the value never actually enters memory but hangs around in the stray capacitance on the bus;" could you elaborate?
    – wizzwizz4
    Jan 14, 2018 at 10:51
  • @wizzwizz4 In dynamic RAM, each storage cell is basically a small capacitor holding a charge representing the state of cell. As a capacitor is basically two conductors separated by an insulator, almost every part of a circuit also acts as minuscule capacitors, including the bus lines. This means that if you just wrote a value and immediately re-read it, this capacitance influences the value read, and may even dominate/hide any charge leaking within the actual malfunctioning storage cell. Wait sufficiently long for the stray capacitance to no longer dominate, and your read might change.
    – Retrograde
    Jan 14, 2018 at 13:54
  • Paul Rickards regularly tweets about replacing DRAM chips in retro computers, with screen shots of the bizarre symptoms in many cases. Jan 14, 2018 at 14:34
  • @StephenKitt If you can find anything not covered in this answer, that would be grounds for another! :-)
    – wizzwizz4
    Jan 14, 2018 at 14:37
  • If a DRAM can hold a variety of patterns for much longer than the normal refresh interval (i.e. with the normal refresh mechanism disabled or slowed down) without losing data, that would tend to suggest that it's good. It's possible to reconfigure DRAM refresh timing on the original IBM PC, but on a lot of other micros it isn't.
    – supercat
    Jan 9, 2020 at 7:24

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