To understand how Amiga memory bandwith should be calculated and how data fetching to Amiga Chipram works.
The timingslot schematic that rwallace refering to does not tell anything about how individual chipram ic' operates or are supposed to operate;
it just explains how the Amiga timing system is layed out.
The Amiga is a synchronized multiprocessor platform/architecture. It share same memory to some extension.
That shared memory is called chipram.
The shared memory require some rules to be followed to make it work and to avoid something called bus contention.
Bus contention occurs when more than one processor want access to the common address-, data-, or registerbus.
To solve this Amiga has a nested (interleaved) access to the buses (and some other solutions too).
It means that the bus access is divided into odd and even timeslots.
The whole timeslot concept is based on duration of one video raster-scanline, and that one timslot has a duration of approximatly 280ns.
Why 280ns? Because it's the speed of the color clock driving the amiga chipset (Agnus, Paula, and Denise. Agnus contains the DMA controller
responsible for memory access to chipram).
1000 000 000 / 3546895hz (colorclock) = 281.9367ns (PAL)
Due to the interleave approach to solve the bus contention problem the individual processors does not fetch data from chip memory with a bandwidth of 7mb/s but instead
half of that amount - 3.5mb/s. Now this it not the whole truth. In graphic intensive tasks the amiga chipset can take full control of the buses
and run at full bandwidth (7mb/s) at the expense of the cpu not having any access at all (no timeslots to its disposal). The DMA sytem can also be turned off and let the cpu have
full access and do all the work (every other timeslot that is).
Note: horisontal and vertical blanking period is not included in these situations.
To calculate the memory bandwidth for the cpu (mc68000):
Following calculations applies to OCS/ECS (16-bit) chipset:
- Master clock (MC): 28.37516Mhz (PAL), 28.63636Mhz (NTSC)
- Color ClocK (CCK): MC/8 = 3.546895Mhz (PAL), 3.579545Mhz (NTSC)
- CPU speed is (MC/4): 7.093790Mhz (PAL), 7.159090Mhz (NTSC)
- It takes 4 cpu cycles for main cpu (Motorola 68000) to fetch data from external memory (Fast or Chip mem) -->
7.093790Mhz / 4 = 1.773448Mhz (PAL),
7.159090Mhz / 4 = 1.789773Mhz (NTSC)
1.773448Mhz * 2byte = 3.546895mb/s (PAL)
1.789773Mhz * 2byte = 3.579545mb/s (NTSC)
It actually takes 560ns - two time slots (one time slot being 280ns)
for cpu to fetch data from memory (Fast OR Chip mem).
- 1000 000 000 / 7093790Mhz = 140.96837ns
- 140.96837ns * 4 cpu clockcycles = 563.87347ns
How much is the different clock-speeds in terms of nanoseconds (ns)?
Always divide the (Mhz) by 1000 000 000 (1000 000 000 / Mhz) and you will get ns.
When you read the inscription on memory ic's the access speed is written in nanoseconds e.g. 41256-15 means 150ns (access time).
To increase bandwidth to chip memory three 'rules' must be fulfilled:
- Cpu clock need to be synchronized with masterclock.
- Chip memory need to be fast enough to handle the new clockspeed.
- The cpu clock need to be at least four times as fast, i.e. at the same speed as masterclock to double the bandwidth. The synchronization require cpu clock to be a multiple of masterclock.
Why does cpu need to be four times as fast to increase the bandwith?
Because of the interleaved approach to chipram between cpu and amiga chipset; this together with the fact that - as mentioned above - it takes 4 cpu clock cycles to fetch data from chipram (and fastram). In other words; cpu access chipram (and chipregisters) every other timeslot and therefore it needs to be quadrupled in clockspeed.
NOTE: This will only increase bandwidth between cpu <-> chip-ram and not the speed between Amiga Chipset <-> chip-ram.