Brief look shows that you use [A15:A8] in circuit feeding CS pin; Z80 is having only 256 distinctive ports controlled by OUT command family, thus you must drop [A15:A8] out of the equation. Please look into the Z80 manual/datasheet here, you will find the following:
The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. The contents of Register B are placed on the top half (A8 through A15) of the address bus at this time. Then the byte contained in register r is placed on the data bus and written to the selected peripheral device.
In your current setup you do not need contents of register B. As B is most probably is not zero defined by
ld bc,AY3891X_LOCATION+0x3, your CS signal does not activate.
Depending on value of
AY3891X_LOCATION you may just be writing to the wrong port. /CS pins is active low, thus per your current PLD equation correct port range is 010h to 017h (not consideting [A15:A8]).
that's unfortunatly probably working
You must make it right, not probably right? You are lucky that this code works in this configuration; if B will happen to be other than 0 it will stop working.
Next, formally you have no output on the /RESET wire. You just connect two inputs on the circuit.
You must draw proper circuit diagram, with pin numbers and all connections. I bet you will find a mistake when doing it.
Update: I used to use AY8910; this AY8913 is having /CS pin, and there's nothing in the datasheet on the timing of this pin, and there's almost nothing about which event actually writes data into the chip's latch.
/CHIP SELECT (Input): pin 24 (AY-3-8913 only)
This input signal goes low to enable the PSG to read data on the data bus or write data from the data bus to one of the internal registers. For these above operations to occur, this signal must be true in addition to the current bus address being a valid PSG address. This signal must be valid for all read and write operations. This pin has an internal pull down to Vss.
Readable web source
There's high probability that /CS signal goes inactive before BDIR and BC1 change (Z80 holds valid address for some time after deactivating /IORQ); thus if we imagine that write to PSG is performed on change of BDIR/BC1 to inactive state, then removing /CS before changing BDIR/BC1 will cancel the write operation.
As a test I recommend you to pull /CS low (or leave it unconnected as it has internal pull-down);
in your current setup there should be no false positives no I am wrong here, there will be false positives because A0/A1 reading the ROM will drive PSG malfunction.
I am afraid you will have to rewire BDIR/BC1 to the PLD and mix them with IORQ in there so that they go to INQACTIVE state (00) for PSG when IORQ is deactivated.
I still don't understand why it wouldn't work before though. BDIR is always 1 when CS is active so it wouldn't go to INACTIVE (00) right?
Glad that it works now. If you did what I recommended above, you have CS low (always active), and operation of PSG is controlled by the BDIR/BC1 signals. They must be of some specific combination to start operation, and changed to other combination (I guess to 0/0) to finish operation.
Thus to latch address you must set BDIR/BC1 to 1/1, and when you switch to 0/0 (inactive mode) it stores the address. To latch register you set them 1/0, and then change to 0/0 and store happens. With read it should be differently, you change from 0/0 to 0/1 and data appears on data pins within specific timeframe.
When you had /CS controlled, it was a combination of (/IORQ) OR A3 OR (NOT A4) ..., and was deactivating when /IORQ goes inactive. It happens before A1/A0 (in your case BDIR/BC1) transition from 1/1 or 0/0, thus chip appeared to be deselect before actual write operation is initiated.