When an interrupt happens on a PDP-10, as on many other architectures you get the program counter pushed onto the stack. Actually, the program counter includes many status bits in the upper half of the word, similar to early ARMs.

One of these bits is the "First Part Done" bit, which apparently may be set to 1 or 0 depending on if something was done or not.

My question is about that bit. What is the First Part of executing an instruction? Why service an interrupt after that thing, instead of after the entire instruction?

3 Answers 3


The First Part Done bit is used to signal whether a specific part of an instruction (the "first part") is done already or not.

It is only set on instructions like ILDB ("Increment and load byte") and ILDW ("Increment and load word") that address a pointer to a byte/word in memory, increment that pointer, and then fetch the byte or word that is referenced by that pointer into a register.

My guess is the FPD bit simply signals whether the increment has been done yet or not, as the interrupt might occur before or after the increment has been done (this seems to be a sort of "non-atomic" machine instruction).

Outside the CPU itself (for example for a program) this bit has no use whatsoever according to the manuals. It simply tells the processor where to pick up after a return from the interrupt.

  • Alternatively, the FPD bit could signal to the kernel that the first part of the trapped instruction must be rolled back before returning from the interrupt. This would simplify the hardware at the cost of a few instructions in the kernel. Which way it was actually implemented would be completely transparent to a user program.
    – Leo B.
    Commented Nov 19, 2018 at 23:18
  • 1
    The PDP-10 doesn't have an ILDW instruction. Commented Apr 10, 2019 at 11:58

IIRC, this was set during very CISC-y instructions that could take many dozens of machine cycles and/or memory accesses. It was set so that if a page fault or other high-level interrupt occurred while the instruction was executing, the CPU would know not to restart the instruction from the beginning (although I'm a little hazy about how it knew where to restart it from if FPD was set).

  • In the days before atomic instructions?
    – RonJohn
    Commented Apr 8, 2018 at 23:53
  • It's really about multiple memory cycles used by one instruction. Some interrupts were so urgent that delaying a few cycles would prevent the interrupt from being serviced in time. Keep in mind that some devices, like DECtape, had no separate path to memory. Commented Apr 11, 2018 at 20:08
  • My first exposure to the FPD bit was with VAXes, and in that realm you could have single instructions (e.g., POLYG, evaluate a polynomial with G_FLOAT [64-bit] precision) that would require reading many bytes of memory, and it was to be expected that some of those bytes might cross a page boundary, with a resultant page fault.
    – TMN
    Commented Apr 12, 2018 at 13:04
  • Also on the VAX: long running instructions (MOVC3 for example) are interruptible. Intermediate state is saved in the general registers (several of which are going to be modified by this instruction anyway). FPD tells the microcode to use the intermediate state.
    – dave
    Commented Nov 19, 2018 at 12:56

Just a quick supplement to the other answers.

The PC does not get pushed automatically. When an interrupt happens, the processor operates in a special mode where instructions are fetched but the PC stays the same as before the interrupt. If you want the PC saved (which is not always necessary), you should use a JSR instruction to explicitly do that.

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