In terms of a modern CPU:
The 36 double-precision MFLOPs that @Raffzahn mentions for a CDC 7600 (1969) is about equivalent to a single-core 2.25 MHz Haswell or Skylake (not GHz). i.e. less than one thousandth of a single core of a modern desktop/laptop Intel CPU at 2 to 4 GHz, with theoretical max FP throughput.
Pentium MMX is not a great comparison: its FPU is weak compared to modern x86. It was fully pipelined 3c latency / 1c throughput
fadd / etc. (https://agner.org/optimize/ instruction tables), but in-order execution plus the x87 stack register design made it hard for compilers to take advantage, and the x87 stack registers often required extra
fxch instructions which hurt practical throughput. Modern x86 has SIMD, and even scalar FP is done with SSE2 using a flat set of registers.
Theoretical max FP throughput on Pentium / Pentium MMX is not bad at 1 FLOP per clock, but @Raffzahn is using much more conservative numbers which puts a 150 to ~200MHz(?) Pentium at 36 MFLOPs for some practical benchmark.
Skylake's absolute max FP throughput is 16 DP FLOP / clock, using AVX and FMA. (2x 256-bit SIMD vector FMAs per clock, counting an FMA as two FP ops: a multiply and add). Or 32 single-precision FLOP / clock, because twice as many elements per SIMD vector.
It's hard to take advantage of this much FP throughput without bottlenecking on the front-end or load/store throughput, but a well-tuned SIMD matmul can come pretty close. Most other code can't come close; maybe a factor of 10 lower FLOPs would still be fairly reasonable for some code, especially if it's not compiled to use FMA instructions.
(This is without considering AVX512, which on CPUs with two 512-bit FMA units doubles the theoretical max FLOP / clock throughput.)
I don't know how hard it was to write code for a CDC that actually bottlenecked on its peak FP throughput, rather than memory, instruction-throughput, or something else.
I'd guess that modern x86, especially Intel, has a lot more raw computational throughput available relative to other system bottlenecks, so it's harder to get close to theoretical max throughput in "normal" code. (modern AMD has about half the raw FMA throughput per core per clock vs. Intel). FP computation throughput has grown even faster than most other throughput resources, comparing a Pentium MMX to a modern Haswell/Skylake for example.
But still, I think we can be pretty confident that most FP code compiled for a modern x86 will usually run at least 100 times faster than when compiled for a CDC 7600, even without spending a lot of effort manually vectorizing. Some tuning for cache sizes / contiguous memory access may make a much big difference on modern CPUs than on older ones: good/bad memory access patterns are critically important for CPU cache to hide DRAM latency/bandwidth. The mismatch between CPU and RAM speed has grown a lot since the 1970s, and the round-trip latency is hundreds of core clock cycles these days.
(Compilers have advanced a lot since then, too, in terms of loop optimizations and FP transformations, especially if you compile with
-ffast-math to allow the compiler to pretend that
(a+b) + c is equivalent to
a + (b+c) and similar approximations that FP rounding error makes not quite true.)