Why did early versions of the 65C816 CPU need a suffixed NOP to every SEP and REP instruction? I saw comments in some source code pointing at this. Looking around in official WDC's documentation and others didn't reveal even a hint on this subject.
The original 65816 layout was done by hand and was not amenable to high speeds. In particular,
PLP as well) instructions didn't complete in 3 cycles when overclocked. (Even today, the data sheet notes, "the MX [pin] output is invalid during the instruction cycle following REP, SEP and PLP instruction execution").
The Transwarp GS accelerator stretched clock cycles to work around that problem.
In 1992, a Sanyo redesign fixed the issues and enabled higher speeds.
(Sourced from comp.sys.apple2 archives and GEnie A2 Transwarp GS archives)
I am not an expert on this processor or its history but this sounds like the sort of silicon bug that I have had to deal with on many processors over the years. It is often the case that there are timing problems with early versions of the silicon for a given processor that then require a software workaround. These are normally detailed in a processor errata sheet published by the device manufacturer. Typically compiler writers will fix their code generators to produce code that adds any extra workaround instructions automatically, some even have compile time switches that allow the programmer to specify which silicon revision their code is to use. If the workaround is simple than the problem may never be fixed and it just becomes a "feature".
I have looked for a WDC errata sheet for their processor but without success.