Why did early versions of the 65C816 CPU need a suffixed NOP to every SEP and REP instruction? I saw comments in some source code pointing at this. Looking around in official WDC's documentation and others didn't reveal even a hint on this subject.

  • Are you able to cite any source code that does this? Commented Jun 25, 2018 at 15:07
  • The original comment was "NOP necessary for early versions of '802/'816 >4MHz.", mentioned in a source code of a Forth implementation which is not publicly available. A connection to a timing issue seems obvious ... Commented Jun 25, 2018 at 15:50
  • Fourth hand info from usenet: "one of the engineers from AE once told me that Mensch had told him that the problem with certain instructions not working at high speeds was the physical distance that some of the signals had to travel inside the chip. ". I vaguely recall hearing GTE fixed some problems and those changes were incorporated back into faster CPUs. Commented Jun 25, 2018 at 18:31
  • Another usenet post (comp.sys.apple2, 1990): "Bill Mensch did a good job on the instruction set, but his mask leaves a lot to be desired since it does not lend itself to high speed operation. Unless they've fixed things, on the 8 mhz parts REP and SEP take 250 ns to operate so you have to put a NOP after each one OR you have to stretch the clock the way the transwarp does. WDC has admitted that this is caused by very long signal lines." Commented Jun 25, 2018 at 18:37
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    @KelvinSherlock. That seems like an answer to me. Commented Jun 26, 2018 at 4:04

2 Answers 2


The original 65816 layout was done by hand and was not amenable to high speeds. In particular, REP/SEP (perhaps PLP as well) instructions didn't complete in 3 cycles when overclocked. (Even today, the data sheet notes, "the MX [pin] output is invalid during the instruction cycle following REP, SEP and PLP instruction execution").

The Transwarp GS accelerator stretched clock cycles to work around that problem.

In 1992, a Sanyo redesign fixed the issues and enabled higher speeds.

(Sourced from comp.sys.apple2 archives and GEnie A2 Transwarp GS archives)

  • SEP and REP are two-byte instructions which perform an operation which is nominally simpler than ADC #imm, which takes 2 cycles in 8-bit mode. It would thus be logical for SEP/REP to take 2 cycles. The fact that it takes 3 (according to current documentation) suggests that the "fix" was to add an extra cycle, effectively building the NOP previously required into the instruction itself.
    – Chromatix
    Commented Jul 1, 2018 at 8:57
  • They took 3 cycles in old documentation (dating back to 1985) too. That's a good point and it very well could be that, during development, WDC increased the cycle count to compensate for a poor layout. Commented Jul 6, 2018 at 22:12

I am not an expert on this processor or its history but this sounds like the sort of silicon bug that I have had to deal with on many processors over the years. It is often the case that there are timing problems with early versions of the silicon for a given processor that then require a software workaround. These are normally detailed in a processor errata sheet published by the device manufacturer. Typically compiler writers will fix their code generators to produce code that adds any extra workaround instructions automatically, some even have compile time switches that allow the programmer to specify which silicon revision their code is to use. If the workaround is simple than the problem may never be fixed and it just becomes a "feature".

I have looked for a WDC errata sheet for their processor but without success.

Example MSP430 errata sheet from Texas Instruments

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