I have looked this video - Altair 8800 - Interrupt Acknowledge Cycle and have few questions (I have read wikipedia Intel 8080 article, Altair 8800 Operator's manual, Charles Petzold "Code" and few article on the internet, like this and didn't found answer yet):
Maybe to start with the obvious: Not every device needs to be interrupt driven.
- Altair 8800 (and Intel 8080) have 8 RST, the first, RST 0 used by hard reset button, so only 7 RST we can use for peripherals (I think). Does it mean, that it couldn't be connected more than 7 peripherals to this computer? Because, how it will be work, if the CPU doesn't notice it?
No, all it means that there are only 8 distinctive routines that can be called directly by issuing one of the RST instructions. It doesn't imply any relation to the number if interrupt serviceable devices or devices at all.
(And it's 8, not 7, as RST0 can ofc be used for an interrupt handler)
An interrupt controller (like 8259 *1) can issue one RST for all interrupts, having them all initiate the same routine and then be polled by the routine to check which is the one to be served. Or they can have separate. Or a mixture of both. It's up to the systems requirements (and what style the designer preferred).
Or, instead of an RST, a CALL can be delivered (*2). When the 8080 (or Z80 in Mode 0) senses a CALL opcode during an interrupt cycle it will issue two additional cycles to fetch the address to be used. Thus there can be as many different entrypoints as one wishes (*3)
- Why Intel 8080 have 256 I/O port addresses, while it has only 8 RST instructions to handle 8 devices? How is it supposed to work with the other 248 devices?
As said above, number of RST instructions, number of interrupt sources and number of I/O ports are not in any predefined relation to each other and to the number of 'devices'.
To start with, there is no assumption if a device is represented by a single I/O address, or if it occupies several. A 8251 serial interface would occupy 4 I/O addresses, while a 16550 needs 8, and a 8250 can get alone with just two.
In fact, one I/O address could as well be shared by multiple devices due to whatever (hardware or software) protocol. Like accessing different devices when writing or reading.
Next, a 'device' does not need to have an interrupt associated. It may or may not, depending on its purpose, structure and workings. This may even differ for the same type of device. For example a keyboard interface can be implemented interrupt driven - with issuing an interrupt for each keypress, or polled, where it' up to the CPU to look if a new keypress has occurred or not.
And last, an interrupt can be shared by two devices - like having a board with several 16550 sharing a single interrupt line, programmed to use the same RST. Resulting in one interrupt, one RST, two devices and 16 addresses.
- Does each RST "hardwired" to specific socket on the S-100 bus?
(I assume you mean Slot when speaking about 'Socket')
No. The S100 bus (in actual use, not as with the original Altair) supports three interrupt lines: /RESET, /NMI and /INT which connect all slots in parallel. Ignoring /RESET and /NMI, there is only one line, thus there can not be a slot specific assignment (*4). It all depends on the CPU used, the interrupt mode used and programming of the interrupt controller used.
But as there is only one interrupt, it is the same for all devices. The routine is selected by what instruction is placed on the bus during an interrupt cycle by the interrupt controller. In case of an 8080/85, it will be one of 8 possible RST instructions inserted by the 8259 interrupt controller as well an arbitary CALL instruction. In case of a Z80 (Interrupt Mode 3) it might also be one of 128 vector numbers.
Now, if your question is about the 8 seperate interrupt lines usually called
VI7, then again, they are shared between all boards and it's up to the system configuration if they get assigned to seperate boards (usually by jumpers) or get used by multiple - in both cases again, they can be used by one or more devices on these boards. Wellcome to the wonderful world of S100 bus configuration :))
Remember there is only one interrupt line on the CPU, so handling 8 lines from the bus means, that there must be an interrupt controller (8259) on the CPU board to encode and prioritize them. Otherwise they might be a bit hard to handle.
- How the device port number are determined? That is, why the keyboard in the video has the 20Q port, why not 1Q for example? Is it caused by the socket number, the device type, something else?
(Not sure what 20Q or 1Q should mean here)
As said, the assignment of I/O addresses to 'devices' is arbitrary and decoded at each I/O board. (hopefully) The right board will respond to an address (if not we got a configuration error). The assignment is usually hard coded or can be selected from a predefined range by jumpers. On the software side it depends as usual on the software used. It may be hardcoded in the drivers (BIOS) or due some kind of configuration file.
After all, that's why a system abstraction like CP/M is so handy as all these codings are hidden below and user programs only interact with symbolic devices.
Confused? Well, interrupt handling isn't the easyest lesson to learn when about a CPU, especially not with rather sophisticated mechanics like on the 8080/Z80 family. Just take your time an gnaw thru all the paper :)
*1 - Usually the 8259 is associated with vectored interrupts (RST or CALL). There are other chips, like the 8214, but they lack the ability to issue different vectors (or vectors at all).
*2 - IIRC, any instruction can be issued, but only RST and CALL do make sense under normal circumstances as they both do a proper subroutine invocation. Then again, with a careful design other instructions could be useful in the right situation.
*3 - Within the reasoning of a system with only 64 KiB address space of course :))
*4 - Keep in mind, S100 is a simple parallel bus utilizing an undefined number of slots. None is prioritized or special in any way. Any card can be placed in any slot. Much like the PC bus system. In contrast the Apple II bus uses geographical addressing, meaning while each slot is electrical the same (lets ignore #0 and #7 for this), they will be seen on different address ranges by the CPU. That would be geographical addressing - which S100 is not.