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As discussed in some previous questions here, 80-column text was established by IBM as the standard for business computing as early as the sixties, but monitors capable of displaying that resolution legibly were still somewhat expensive in the seventies, so early microcomputers that used TV sets, or monitors with off-the-shelf TV tubes, such as the trinity of 1977, settled for a lower resolution: 40 columns for the Apple II and Commodore PET, 64 columns for the TRS-80.

As I understand it, a black-and-white TV tube with no color burst signal and the RF stage skipped, while it could not quite reach 80 columns, could handle 64 columns well enough, which raises the question of why Apple and Commodore didn't try for that, or at least for something a bit beyond 40. 64x25 = 1600 bytes, not prohibitive even by the standards of the time.

I get the impression memory bandwidth was a significant limitation, such that when the Apple II later added an 80-column option, the engineering of such involved the careful juxtaposition of two memory banks to provide data at the required rate.

Was memory bandwidth the reason for Apple and Commodore sticking with 40 columns? If so, how did Tandy achieve 64 columns? Is it purely a coincidence that the 64-column machine is the only one of the trinity to use the Z80?

(I'm assuming the Vic-20 later supplying only 22 columns, is not so much due to technical limitations as to the use of a video chip designed more for games than general purpose computing.)

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    Two idle thoughts: 40×25 fits neatly into 1 KiB of memory; and many of the 8-bit systems of that generation (Apple II, PET, Atari 8-bit) were designed for 4 KiB of RAM as a base configuration, even if they were never sold like that, which doesn’t leave much room if you start expanding the character buffer. (Of course it would have been possible to plan for higher-resolution modes, but I get the impression such considerations were unusual in the micro world back then.) – Stephen Kitt Jun 26 '18 at 13:32
  • The way the c64 and probably PETs were designed, more columns would have meant a faster CPU and also faster memory. It might have been impossible. – Wilson Jun 26 '18 at 14:54
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    Note that 80 columns requires non-square pixels to avoid flicker on an interlaced screen. So b&w with non-square pixels requires a special video mode which adds complexity to the video signal generator, for which you need a b&w screen anyway. It almost makes sense to create separate computer product lines for home and business. In fact, Steve Jobs resisted adding color to the Mac line because he wanted it to remain a business computer. – traal Jun 26 '18 at 15:05
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    The Vic-20's column count is entirely a product of a bandwidth limitation; it actually has and uses much the same bandwidth as a C64 but doesn't have the ability to capture a line of character indices upfront. So half as many characters in the same horizontal space, but also no need to be as prescriptive about how many characters so the display is a little wider. – Tommy Jun 26 '18 at 16:07
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    The notion of 80 column records goes back a bit further than the 1960s. en.wikipedia.org/wiki/… – Solomon Slow Jun 26 '18 at 16:58
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Don't underestimate the cost of additional RAM for display memory!

The TRS-80 used seven, not eight, 1x1024 static RAM chips for its display memory. They left off the eighth chip to reduce cost. Without it, the machine was limited to uppercase-only display -- one bit per character cell to specify whether that cell displayed a character or a 3x2 graphic tile, and the other bits to specify the character or the state of each graphic block.

It was common to solder an eighth chip piggy-back onto one of the existing display chips. Once you connected that extra data bit to the bus, you could display lowercase -- the character ROM already had lowercase characters and special symbols in its map, it just needed the data to drive it.

At the time these machines were introduced, I think a static 1K chip was still a few bucks. That's a significant chunk in a product like this. It would also have required more board space; in those days of medium-scale TTL DIPs, dual-layer boards, and coarse design rules, each additional part took up quite a bit of room. Bigger board, more expense.

Now, imagine doubling the amount of display RAM, and requiring a more expensive higher-bandwidth monitor. In the late 1970s, it just didn't make economic sense.

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    This is likely to be it more than bandwidth in my opinion; the Apple II is maxing out its bandwidth with the no-sparkle shared bus but if memory serves then the original PET requires a programmer just be careful to leave the video memory alone during the active period. But by my calculation, RAM that's fast enough for a 1Mhz 6502 is fast enough for an 80-column display if permitted to dedicate itself solely to that task. More than fast enough since you can be lazy with RAS. – Tommy Jun 26 '18 at 16:22
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    @Tommy Good point about having enough bandwidth if the CPU doesn't access memory during active scan line. Now I remember the TRS-80 suffered video glitches when the CPU did so; presumably they didn't have time to design arbitration logic to prevent this. That would explain how that machine got more than 40 columns. – rwallace Jun 26 '18 at 16:38
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    The TRS-80 has 64 columns by 16 rows, which requires essentially the same amount of display memory as 40x25. Including a bit to select graphics but not one to select lowercase/reverse video seems a curious choice, though. – supercat Jun 26 '18 at 16:58
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    @rwallace IIRC the "arbitration logic" was "if the CPU is accessing video memory when the video circuitry reaches for a byte, feed a value of 0 to the video circuitry." 0 generated a blank (black) cell, so that particular ROW of that particular CELL would show up as black on that particular refresh. End result: when PRINTing stuff to the screen in BASIC, you'd see dark one-pixel-wide horizontal lines flickering on the screen. When you scrolled the screen (block-copying stuff in video RAM), you'd see more flickering (higher duty cycle hitting that RAM). – jeffB Jun 26 '18 at 19:40
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    @supercat: Yeah, but that ROM was a canned part from Motorola, the MCM6670, prepackaged in an 18-pin DIP. link There was presumably no money to be saved by doing something custom. As for an extra RAM chip and a few more gates, IIRC we actually hijacked unused gates already on the board for the needed logic, but that chip was pure extra cost and footprint (unless you piggy-backed it, which wasn't very manufacturable). – jeffB Jun 26 '18 at 20:11
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This answer has the Commodore 64, the Amstrad and the Sinclair ZX Spectrum and QL series in mind.

Note these home computers did not have a real "text" mode (as opposed to the more professional systems like IBM MDA, for example).

This means text needs to be displayed as graphics, and graphics needs resolution. A reasonably readable text font needs at least 5-6 pixels horizontal (business use would have required 8), and 8-10 pixels vertical size (including blank pixels to separate the characters from each other). Multiply that by 80 characters and you end up with resolutions >400 pixels horizontal, >200 vertical, which means at least 10k (better 16) of video memory, even with monochrome text, even more if you want more readable fonts, way more if you want at least four colors for your text. The Sinclair QL spent 32k of its scarce 128k for the video frame buffer, enabling it to display 85 characters by 25 lines in four colors.

With memory sizes from 16k to 48, maybe 64k on a typical home computer, 16k are not easily expendable.

That was the one reason - Another one is, once you got the pixels in the frame buffer, you need to get them out onto the screen - once every video frame, you need to clock out all the pixel data to the monitor. While this is done, the video circuitry needs exclusive access to the framebuffer and, in principle, halts the CPU (on simpler designs like most home computers, on more complex designs, the lockout of the CPU may be restricted to the framebuffer and it would still be able to work on other memory).

This means that the higher the screen resolution gets on such simple designs, the more the CPU needs to wait for access to the memory because it is locked out by the video circuitry (so-called "contended memory"). Some designs get across this using dual-ported memory, or dedicated memory chips for the frame buffer, but that is expensive.

Displays that work with a pure text mode storing characters in the frame buffer do not have this problems - Their video memory is much smaller (it doesn't need to store the pixels of a character, but rather only one byte for it's ASCII code), also their video output needs way less memory bandwidth. But again, home computers wanted graphics and a switchable graphics/text mode again uses circuity and thus costs money.

In the end, most 8 bit home computers restricted themselves to resolutions not much larger than 600 x 200 for these reasons.

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    'Note most home computers did not have a real "text" mode' - the Spectrum and Amstrad didn't, but every other 8-bit computer I can think of did. What other exceptions am I missing? – rwallace Jun 26 '18 at 15:06
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    @rwallace The Acorn Electron, in some sense the BBC Micro, the Oric, the Sam Coupé, the Sharp MZ-800 and many, many more – tofro Jun 26 '18 at 15:20
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    @rwallace You can pull the character data from an off-bus character ROM without consuming any bandwidth - That is what the IBM MDA did. – tofro Jun 26 '18 at 15:22
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    @Tommy Bandwith is decreased if the pixel fetch of the CRT controller can be made off-bus (maybe from a character ROM). Obviously, you're losing the possibility for user-defined characters, then. – tofro Jun 26 '18 at 16:36
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    @Tommy: Reducing bandwidth also requires that characters which are fetched from RAM be held in some kind of buffer that can be replayed multiple times. The Apple I video hardware did this (it actually used zero bytes of RAM to hold the display contents; the bulk data was held in six 1024x1 shift registers and the current line was held in a 40x6 shift register. – supercat Jun 26 '18 at 17:04
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As I understand it, a black-and-white TV tube with no color burst signal and the RF stage skipped, while it could not quite reach 80 columns, could handle 64 columns well enough,

It can do 80 as well, but that's already borderline.

which raises the question of why Apple and Commodore didn't try for that, or at least for something a bit beyond 40. 64x25 = 1600 bytes, not prohibitive even by the standards of the time.

As Stephen Kitt already mentioned, 1 KiB is a lot of memory, especially considering that the early machines like PET and Apple II were meant to work with as little as 4 KiB total RAM. The 'mere' 600 bytes needed for 64x25 would have been a rather deep cut.

Where Commodore and Apple stayed with a 'traditional 24/25 line display, Tandy did go a different way by making the screen 'binary' compatible with a 64x16 resolution - thus staying within the 1 KiB needed for display memory but showing longer lines.

I get the impression memory bandwidth was a significant limitation, such that when the Apple II later added an 80-column option, the engineering of such involved the careful juxtaposition of two memory banks to provide data at the required rate.

Not in any way. Simple math tells that a 1 MHz machine with video a video access window on every clock can deliver 1 MB/s. A 40x24 screen at 60 Hz needs less than 60 kB/s, that's less 6%. There's much room for a larger display, even when including other constraints like frame structure.

The problem with the Apple II was that its timing is built around the video timing. The CPU doesn't get a monotone clock rate, but a varying one to make it fit. While this was a quite clever design, it's somewhat inflexible when data needs to be accessed at double the rate. Ofc, they could have went along and redesigned the whole timing - or doubled the machines speed (which would have been nice). The least intrusive way to double accessed data within the existing timing was adding just another KiB and make video access 16 bits wide.

Was memory bandwidth the reason for Apple and Commodore sticking with 40 columns?

No. On the Apple side it's rather clear that WOZ intended the use of a TV set with (or without) intermediate RF. Thus 64 would be out of scope and 40 seams a nice thing.

For the PET, I can only guess that they tried to stay on the safe side (*1) - and, maybe more important wanted to keep 24 lines. With 24 lines 42 would have been possible - but that's really odd, isn't it?

We often forget here the other early machine, the Atari 400/800. Here, like with the Apple, a standard TV set was intended as main display, so 40x24 is a logical choice.

If so, how did Tandy achieve 64 columns? Is it purely a coincidence that the 64-column machine is the only one of the trinity to use the Z80?

As soon as one is willing to diverge from the 24/25 lines paradigm, 64x16 is a quite reasonable choice. Especially when it comes with an 'internal' screen

(I'm assuming the Vic-20 later supplying only 22 columns, is not so much due to technical limitations as to the use of a video chip designed more for games than general purpose computing.)

I think that's a good assumption.

Much like the TI 99/4 was designed around the use of a TV set. Here the standard mode was only 32x24 (a two color 40x24 was also available).

The C64 later on benefited from the 40x24 decision for the PET.


*1 - I would like to think that they did keep an eye on the use of a TV during design - and before the decision was made to produce an all-in-one unit.

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    Minor nit pick, not a big deal: unless you're assuming intermediate buffering, shouldn't the bandwidth calculation for a text screen be computed as bandwidth while painting pixels multiplied up? So e.g. the absolute least bandwidth necessary for a 40-column display would be 40 bytes in 52 microseconds, if you were risking using the entire "visible area" of the signal? Which I actually make about 770kb/sec. Then probably a bit more to allow a reasonable border. – Tommy Jun 26 '18 at 15:57
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    Good points! Upvoted. But I'm not so sure about your reasoning on this point: 'A 40x24 screen at 60 Hz needs less than 60 kB/s, that's less 6%'. Overall per frame yes, but that way of measuring it assumes the video chip can cache a whole frame buffer, which it definitely could not. Even caching a line was by no means guaranteed to be available, not when cache costs over 50 transistors per byte and early microcomputers often didn't have an ASIC video chip. And if no cache and you look at the bandwidth requirements within the active part of a scan line... – rwallace Jun 26 '18 at 15:58
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    according to pineight.com/mw/index.php?title=Dot_clock_rates the C64 has a pixel clock of 8.19 MHz at 320px = 40 col text, so if you assume 8x8 char matrix, 40 col text actually saturates the bandwidth on a 1 MHz machine. Maybe the bandwidth could have been increased in 1982, but seems less likely in 1977? Then the question is, how did Tandy break the apparent bandwidth limit? – rwallace Jun 26 '18 at 16:01
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    The C64 not only saturates its bandwidth at 40 columns, but has to take the CPU off the bus for one line in eight during the visible period in order to cache the tile indices for that row. C64 types call them "bad lines". – Tommy Jun 26 '18 at 16:05
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    @rwallace Tandy let the video chain clock through the static video RAM at its native pace. When the CPU needed access to video RAM, it took priority, and the video chain got zero values during the time it was pre-empted, showing up as black streaks. I'm trying to remember if there was a way to detect the vertical refresh interval and read/write only during that, but I think support for that technique was still in the future. – jeffB Jun 26 '18 at 19:50
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The Apple II is the only one of the 1977 trinity to have memory mapped bitmap graphics: 280x192. With a terribly small font 5x3, you could achieve 70 columns by 32 rows using the "hires" graphics mode. Thank goodness there was a plethora of 80 column text cards that came out in the early 80's for the Apple II. The late Apple //e (1983) model had 80 columns builtin, but that was long after the trinity.

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