What was the clock speed of the first generation of the PDP-11 with the KA11 cpu? This sounds like something that should be easily googlable but so far I have found nothing. I'm also interested in what the instructions per clock (or clocks per instruction) was for that.


This link describes the PDP-11/20 as having a speed of 800 nanoseconds. That works out as 1.25 MHz.

Because that speed is the speed of the memory, (which is tightly connected to the speed of the CPU), and because the databus is no wider than 16 bits, that means that the PDP-11 will at most execute one instruction per clock cycle. And that speed precludes other memory accesses, like DMA or instruction operands, use of the stack or immediate data, etc. So many instructions will take somewhere between 1 and 5 clock cycles.


There was no clock. The way it worked was the Unibus and KA11 were intimate. To read a word from the bus, maybe core, maybe something else, the cpu put out address, control bits and data if write, wait some Unibus specified delay nanoseconds, then assert master sync. The slave decoded the master sync, address, and control then read the data or output data with slave sync. The cpu would see slave sync, wait for skew, take the data if reading, turn off master sync and wait some Unibus specified nanoseconds. The slave device slave sync response time set the speed of the transfer. The KA11 took the data through the data path according to the current machine state or instruction. The ALU in the data path had two distinct speeds. If there was no carry, move, bit test, etc, the fast time was used. If there was a carry involved, increment, add, etc, the slow time was used. The two times were set by R and C values on a 74121 dual one shot timer chip.

Bottom line, the asynchronous RC timing in the core memory, and the asynchronous RC timing in the CPU set the speed of the system. There was no 10 MHz oscillator. All the other PDP-11 processors were microcoded and had oscillators. Speed of execution of a program still depended on memory access time.

Remember, core, with a destructive read, required a write to restore the data that was read. In the PDP-8 the CPU did the restore. In the PDP-11 each core subsystem did it's own restore. That made interleave possible. The machine I used had 12K words of core in 3 4K word banks. The bottom 8K words of addresses were split between the two bottom 4K word subsystems. Rather than decoding address bits 13, 14, and 15 to select a memory system bits 1, 14, and 15 were used. Odd words were in one bank, even words in the other. With the program counter stepping through sequential words like mov #32, @#56, the words would come from alternate banks. A core subsystem with an 800 ns read access and a 2 microsecond cycle time allows the second word read to happen while the first word restore is still in progress. A program loop speed would then depend on whether the program was in the first 8k words with interleave or the last 4K word bank (selected by address bits 13, 14, and 15) without interleave.

I don't know whether DEC typically shipped these machines with interleaved memory. Systems with 2 or 4 memories were interleaved at least in some cases by the installing technician.

DMA, using the Unibus, transferred data similarly. The NPR, non processor request, and NPG, non processor grant, transferred Unibus mastership then the the IO device would do like the CPU and read or write. Interleave worked there too if there were multiple sequential words to transfer. If the IO device was run from a 10 MHz clock then the slave sync wouldn't be noticed until the next clock like a microcoded PDP-11/05.

  • What, if anything, did the PDP-11 do to avoid metastability if an I/O signal changed state just as it was being examined? Clocked systems can use double synchronizers, but asynchronous systems would seem like they'd represent a more complicated situation.
    – supercat
    Jul 16 '19 at 21:27
  • If the setup and hold times are always met there is no metastability. The Unibus spec gives delays to make that part nice. During a CPU read from an IO device the data isn't allowed to change. When the slave turns on slave sync the data must remain until master sync goes away. Asynchronous is harder, more details. Jul 16 '19 at 22:33
  • If an I/O device is supposed to report the state of the switch, would the PDP/11 have one address which would cause the switch state to be loaded into an external latch, another that would copy that to a second latch, and a third to read that second latch (which should presumably be stable even if the first one wasn't), or how did they handle inputs that could change at arbitrary times.
    – supercat
    Jul 16 '19 at 22:59
  • 1
    How did the 74121 one shot timer chip determine the time? It must have used some kind of oscillator.
    – JanKanis
    Jul 17 '19 at 9:58
  • 3
    @JanKanis, these are still being made, active products. See:ti.com/product/SN74121 There is no oscillator, resistance and capacitance set time delay. Jul 17 '19 at 12:59

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