I (as so many people before me) am developing a software simulation of the 6502, mostly based on the often cited block diagrams and several other sources of information.
Basically all the components are done and I am in the process of configuring the Decode ROM and the RCL (Random Control Logic), only to find some unexpected behaviour:
DEX affects the behaviour of the CPU, even after its 2 cycles have completed.
Until now it was my understanding that instructions only control the CPU while they are actually being executed.
But, as can be seen in this Visual6502 example, the T0+T2 cycle of an
LDA# right before
DEX looks different from the T0+T2 cycle of an
LDA# right after the
DEX: RCL outputs an additional SB/X, which is necessary to transfer the decreased value back into the X register. So
DEX has an effect AFTER its last cycle completed.
DEX does not seem to have any lingering effect on the decode ROM/PLA outputs however, as they are identical for both
LDA#s, so there must be some kind of hidden state affecting RCL.
How does this work and which instruction groups are affected? Are there any sources going into more detail about this?
Just for clarification. I am not talking about pipelining. Of course, the second
LDA# is prefetched during the last cycle of
DEX (T1). The SB/X signal that confuses me happens one cycle later, during T0+T2, which is the first cycle of actual execution of
DEX has already been wiped from the IR register.