Some variants of the Commodore PET (e.g. the 8000 and 9000 series, as well as some other versions with an aftermarket add-on) produce an 80x25 character display. Their character set is fixed in ROM using an 8 pixel by 8 pixel cell size. At 60Hz, and with typical CRT timings, this means each scan line lasted about 40 microseconds, so the hardware needed to output a total of 2 characters per microsecond.

The PET uses the 6545 CRT Controller chip, a MOS Technologies clone of the Motorola MC6845. Like the 6845 it has a maximum clock speed of 1MHz (and the PET also runs its CPU at 1MHz, so presumably ties the 6545 to the same clock). The CRT Controller addresses one character per cycle, which suggests that the maximum display width the PET should be able to produce is 40 characters.

How did 80 character PETs work? Did they overclock the 6545? Or was there some trick to producing two characters of output in a single cycle of the CRTC?

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    At a guess: one address is used simultaneously against two different RAM chips, to get two characters per 6845 cycle. That'd be exactly like what Apple did when they later added 80-column mode to the Apple II, amongst others. Just a guess though, so not an answer. – Tommy Jul 28 '18 at 11:53

As Tommy wrote in the comment: There are two different RAM chips, one for even columns and one for odd columns. Both are read and latched in one cycle (ESD and OSD bus), and the latched output of each is then used in turn to drive the character ROM (LSD bus).

You can see it in the schematics for the CMB 8032 here (even) and here (odd).

The Apple //e used the same scheme, with one video bank in main memory and one video bank in aux memory.

However, there were simplifcations, like in the Videx Videoterm 80 column card for the Apple II (manual with schematics), which had its own RAM on the card. This avoids the latches and just puts the RAM outputs in parallel, so apparently the RAM could be enabled quickly enough to make this work.

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