This question expands on How does the 6502 implement its branch instructions?
I'm working on a cycle accurate VHDL implementation on an FPGA. I have much of the program logic already written, but I can't wrap my head around how to logically calculate the relative addressing from the branch instructions.
From everything I've read and reviewed, the only outputs of the ALU are: result, alucout, and aluvout. I've read that the flag outputs from he ALU are routed to the control logic, even though it's not shown in the block diagram.
I built a truth table on several different scenarios for offsets, and it seems you can't just use carry and overflow to determine whether or not to carry to the high byte of the program counter. I even thought to move the bit 7 logic from the flags register logic to the alu, and route that to the control logic, but that wouldn't help either.
Some of the resources I've been using are:
Programming the 65816 - Has a section on the relative addressing in conditional branching
So to put all of this madness into a question... How is the (signed)offset calculated against the (unsigned)program counter, and how do you determine if you need to add a cycle to calculate the high byte of the program counter?