6

Can anyone offer some back-of-envelope sort of estimates of what sort of gate count was needed to add a multiplier to 8-bit CPUs?

I ask because I find it a bit odd that the 6809 had one, but none of the other chips of the era did. It seems that B or C models of the 6502 and Z80 would have the opportunity to add this, so I assume there is a good reason why they didn't?

  • 2
    I'm sure you know that some multiplications are equivalent to left shifts. And so the ARM can use a barrel shifter to multiply e.g. by 9 with a single ADD instruction. The CDC 160 could multiply by a few fixed constants (including 10 and 100 decimal) in this way, by really using an adder. But, assuming you're asking about multiplication by arbitrary factors, I don't know an answer to your question. – Wilson Aug 22 '18 at 18:21
  • 1
    Multiply by shift and repeated add is mainly a question of microcode, not gate count. Now fast multiply is a different thing... that can eat up quite a few gates. Also, 8-bit multiply primitives are not that useful if you need wider arguments/results, so the cost/effect ratio isn't that high. – dirkt Aug 22 '18 at 19:14
  • 2
    I doubt the multiplier was the limiting factor since you first have to double the size of the result register and ALU to make it worthwhile to have a hardware multiplier. And the Z80 already had almost as many transistors as the 6809 without any of its performance. – Brian H Aug 22 '18 at 19:33
  • 2
    Well if we focus on the 6502 for the moment, it would seen a single new (M?) register for the upper 8 bits of the result, and a table for the shift-n-add (maybe 512 bytes in a diode array) and you have the basic thing done. You would need the microcode for the loops, but this seems like something that's not TOO large? – Maury Markowitz Aug 22 '18 at 19:38
  • 2
    but seriously, multiplier at that time is a very specialized equipment, like FPU, and if a processor is equipped with one, then it's a dsp. maybe it's easier to connect the multiplier as a co-processor than to integrate it into the instruction set, like MSP430? – user3528438 Aug 22 '18 at 20:31
7

Can anyone offer some back-of-envelope sort of estimates of what sort of gate count was needed to add a multiplier to 8-bit CPUs?

An 8x8 array multiplier build from 6T adders comes down to 8x8x6=384 transistors. With buffers/drivers this easily reaches beyond 400 transistors, maybe even near 600 when latching is needed. Further some decoding (PLA) and execution (random) might be needed, but that's just a few dozen transistors. In total this might increase the CPU by 20%.

The operation needs two 8 bit values as input and yields one 16 bit value. For a 6502 input would be naturally A and a memory operand, but there is no 16 bit register. While storing the lower 8 bits again in Amight sound useful, X or Y could take the upper 8 bits - damaging the ability to use either in addressing. Or a new Extension register would be needed. Not a bad idea in general (*1), but that adds something like another 50 transistors (*2).

I ask because I find it a bit odd that the 6809 had one, but none of the other chips of the era did.

The 6809 is a complete new design, and the next generation after a 6800 or 6502, more in line with upcoming 16-bit processors of the same time.

It seems that B or C models of the 6502 and Z80 would have the opportunity to add this,

These were just faster speed selections, not really new (or enhanced) CPUs.

so I assume there is a good reason why they didn't?

As so often it's the 'why' question. Why adding and complicating the CPU for such a minor add on? Sure, it'll speed up multiplying, but then again, it's not exactly the most needed operation. I can't remember having it used in all the years of 8086 programming. And even on /370 it was convenient, but not really necessary. Usually, multiplying by 2 or 4 is what's needed, and here a shift will always beat a multiply.


*1 - This might open the opportunity for some quite nice new operations, not at least 16 bit load and store, enabling fast movement of pointers (into ZP).

*2 - Renesas for example did not only add an 8x8 multiply and divide instruction to their 6502 (740 Family), but also avoided the addition of a new register by pushing the upper 8 bits of the multiplication result onto the stack - similarly, with a division, the negated(!) remainder is pushed.

  • You're forgetting that you'll need 64 AND gates as well. – Leo B. Aug 23 '18 at 0:14
  • @LeoB. For what? A 6T full adder just needs said 6 transistors. – Raffzahn Aug 23 '18 at 0:42
  • 1
    That's assuming that none of the gates and adders were fused using pass-transistor logic, very commonly done back in the multi-phase-clock NMOS days. – hotpaw2 Aug 23 '18 at 1:47
  • 2
    @Wilson - the undefined opcodes don't have any specific outputs from the PLA, they just trigger effectively random existing lines, which is why they have behaviour that's similar to existing instructions. New behaviour, like triggering a read of a specific register, would need a new output. And because the PLA's structure only allows you to make outputs an OR of input signals, you may also need to add additional outputs that effectively disable other outputs in order to prevent other actions happening by default for the opcode you've chosen for any new instruction. – Jules Aug 23 '18 at 9:57
  • 1
    @Wilson not realy, as the undefined opcode behaviour is exactly due being not defined. For new opcodes, the existing might need new or at least modified columns to open up the 'undefined' space, and then there are the ones needed for the new opcodes. So yes, it would need a few more connections. Anywhere between 1 and like 5 per new instruction. – Raffzahn Aug 23 '18 at 11:11
6

The first production 6809 was fabricated around 3 years after the first production 6502, and thus, according to the Moore's Law rate of transistor density improvements, was likely fabricated using a small enough transistor geometry that more than double the number the number of transistors were available for the same initial die yield and cost, thus allowing room for adding multiply logic to the ALU (9k, vs. around 4k transistors per die).

A fast carry-save-adder (CSA) tree implementation (e.g. not just a microcoded shift-and-add) of an 8x8to16-bit multiplier requires (I'm guessing) roughly on the order of 5 times as many transistors as an 8-bit adder. In NMOS technology of that vintage, a CSA-type multiplier implementation would very possibly not be done using strictly complete logic "gates", but by also using a mix of pass transistor logic plus inverting amplifiers, even thru to the end of the final carry chain.

No reason to add a mul instruction to later versions of the 6502 and Z80 (even if fabricated in a denser more advanced technology node), since software compatibility and cost reduction was the name of the game for those products.

  • 1
    Is your guess about roughly on the order of 5 times a substantiated one? – Leo B. Aug 23 '18 at 6:33
  • Best way to find out is to try to find the multiplier in a die photo of a 6809. – hotpaw2 Aug 23 '18 at 6:40

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.