In the early eighties, you could buy half-bad 64k RAM chips at a discount. Some cost-conscious manufacturers such as Sinclair and Tandy took advantage of this, buying eight such chips to make a 32K memory bank.

Intuitively it seems like this should be possible with other kinds of chips. For example, the VIC-II is a big complex chip for its time; at least in the early days, yield must have been significantly less than 100%. Most of the area of the VIC-II is used for sprites. That suggests the majority of reject chips would be perfectly usable for non-sprite display. Still useless for the C64, of course, but Commodore did (mistakenly, but still did) introduce the C16 as a spriteless lower-end machine. Instead of basing it on the Plus 4, could they not have given it reject VIC-II chips and saved money? But Commodore was a very cost-conscious company that was known to base designs on what kind of chip they currently had in surplus; if they didn't do that, is there a reason I am overlooking?

Similarly the excellent SID (C64 sound chip). Intuitively it would seem a defect in one of the voices, say, should leave the chip still usable with a smaller repertoire in a lower-end machine like the C16. Is there a reason why this was not done?

The one historical case I know of where part-bad chips were successfully sold with reduced functionality (apart from the possibly apocryphal case of Soviet-made CPUs each coming with a list of instructions that particular chip would successfully execute) is the 486, where units with a defective FPU were sold as the 486SX. Are there are any other cases?

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    Are you able to dig out more knowledge about that Soviet CPU? Aug 26, 2018 at 16:22
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    Keep in mind that verification what exactly does not work might be more expensive than the value of the defective chips. Some functions (like: does a sprite show up properly on screen) are really not that easy to test automatically.
    – tofro
    Aug 26, 2018 at 16:35
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    This is not how it worked. Before modern exhaustive chip testing technologies like boundary scan and JTAG were invented in the 90ies, the only way to test a chip was to set a series of test patterns on the input and observe the outputs - These tests rarely broke down the chip into working and non-working functional areas, but rather sorted chips in "passed" and "failed" - And the failed ones simply went to the trash without further investigation. For a simple RAM chip, you could check whether it held storage at least in an upper and lower area and could sell the other half as functional, but
    – tofro
    Aug 26, 2018 at 16:53
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    @rwallace Tofro is perfect right here. Chip testing isn't as easy, even with RAMs its quite some work, and they are incredible simple compared to chips like a VIC-II. I wouldn't wonder if the tests at MOS would have been rather frugal, and the real tests where only done after the whole machine was assembled. It's way lest costly to plug a ROM cardridge into a finished C64 and have a cheap employe check if it seams fine. Remembering ho ingredible high rejection rates and returns of newly bought C64 where does support this.
    – Raffzahn
    Aug 26, 2018 at 17:21
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    The VIC-II chip that shipped in my Commodore 64 had two partially-defective sprites (sprite 0 and one other) whose output was slow to "turn on". At places where a transparent pixel was followed by a non-transparent pixel, the background would show through. One of the CIA chips was also partially defective, with a "real-time clock" circuit that would not advance between seconds and minutes (which made the last level of Raid over Moscow much easier than it should have been, since the timer would never expire).
    – supercat
    Aug 27, 2018 at 18:47

7 Answers 7


For example, the VIC-II is a big complex chip for its time; at least in the early days, yield must have been significantly less than 100%.

Not really, while the VIC-II had a transistor count a bit larger than the original 8µm NMOS 6502. Not a lot, but it was manufactured in a 5 µm process, resulting in a smaller size and higher yield. The 1981 65C02 had almost three times the transistor count of the NMOS CPU, but due to being manufactured in 3 µm, its size was only a little over 1/4th (6 vs 21 mm^2) and 5 µm was already considered outdated in 1980.

Most of the area of the VIC-II is used for sprites.

I wouldn't call the 40 bytes of line buffer insignificant

That suggests the majority of reject chips would be perfectly usable for non-sprite display.

The whole idea of using rejected chips, especially when it's about rather small (even at that time) chips like the VIC, isn't working out in a commercial way. At least not if you're the original manufacturer and/or customer for such a 'less function' version.

Lets assume, for the sake of the argument, that the area used for sprites is one quarter (25%) of the chip, and the failure location is random. So of all chips with only one failure location, only the 25% with that failure can be used as 'without sprites' (again assuming given that it isn't a failure disabling disables the whole chip - like a contact between +5V and ground :)) For chips with two failures it's maybe another 5% that fall in the same area, therefore it isn't worth looking at even higher rates.

Next, this is all in relation to the fault rate of the production. Here it is important that the 5 µm process on which the VIC-II was produced was well proven and established. Not anywhere near cutting edge - that would have been around 1-2µm at that time. I think it is safe to assume that Commodore did get a yield of way more than 80% already at the first run, and they would have been able to get this to 95+% within a few months.

With such numbers there is no business case for the manufacturer to go for 'less functional' versions. After all, at 80% good rate (which is rather bad), the best possible quote (if all failing chips had only a single failure) would be 5%. That's no production number even worth making a different stamp to mark them. Especially, as from a manufacturer's perspective, all to do is reducing the fault rate to improve sales of the main product.

Last but not least, thorough testing slows down production and costs a lot of money - much more when done into every detail like needed to select chips that are still working at a reduced level. Money that is wasted on good chips. So getting quality up and restricting tests to detect faults as fast as possible and then aborting makes the whole production more cost efficient.

From a customer's perspective (in this case the Commodore computer factories), it's even worse, as your ability to build such a machine on a random output quota from the manufacturer of a product he doesn't want to make in the first place. So with every iteration the VIC-II output gets improved, your supply goes away. To further output machines you must go ahead and use full functional VIC-IIs - which would mean that there you earn less money (assuming the final customer pays less for a less capable machine) from the same resource (VIC-II chip production).

[But then why did the 32 KiBit RAM chips surface?]

A simple matter of scale. For one, 64 KiBit RAM chips are about 10 times more complex than a VIC-II, while at the same time their structure is way more symmetric, enhancing the chance that a faults impact is truly local. Even more important, they were produced in (almost) infinitely larger numbers than for example VIC-IIs - just think, each C64 already had 8 of them compared to only one VIC-II. Also there were many more manufacturers. Each of them trying to get their production running and quality up - each of them going through a cycle from many faulty chips to less of them.

Also, fault-wise it was more simple with RAMs, as any chip with only a single fault that is not located in control or interface (which is less than 2% of the surface) can be used as 32 KiBit one - that makes, using the above reasoning, 98% of single faulty and 49% of double faulty. Sounds like a way better quota doesn't it?

It's further a matter of scaling. With many millions of 64 KiB chips, each factory, especially during run up, produced hundreds of thousands of partial faulties, making it a good business for others to buy this waste at next to nothing and spend money in testing and repackaging then as 32 KiBit.

Bottom line, it's about numbers and Commodore wasn't going anywhere near this.

Still useless for the C64, of course, but Commodore did (mistakenly, but still did) introduce the C16 as a spriteless lower-end machine.

I need to object here (even though not part of the core question). The C16 was neither a mistake, nor a bad idea. Its design was meant to counter Sinclair. Delivering a low end machine that could beat the Monster from the Island :)) Serious, the US home computer industry was shocked by the ZX-80/81 and the prospect of an even more capable future colour machine. The TED as C116 was directly set against that - and the C16 only a fast byproduct of a cheaper 'real' computer using VIC20/C64 parts.

Instead of basing it on the Plus 4, could they not have given it reject VIC-II chips and saved money?

As noted above, there wasn't any real business case to save money. More importantly, the TED had a much higher gate count than the VIC-II. Not least due to its 75 (instead of 40) byte line buffer; it also had a 16-bit timer, a sound channel and an I/O port. Except for the sprites, all its graphic capabilities surpassed the VIC-II. While being more complex it was at the same time targeting a way lower priced market, this should tell how little transistor count meant - at least in this region of rather low integrated ones.

Similarly the excellent SID (C64 sound chip). Intuitively it would seem a defect in one of the voices, say, should leave the chip still usable with a smaller repertoire in a lower-end machine like the C16. Is there a reason why this was not done?

Most likely again, not enough failing chips to make it worthwhile. See above.

But more important, it would have meant that the C16 would have had two chips, like the C64, making production way more expensive than it was targeted for. Beside more board space and traces, also another 64 drillings would have been needed, well, plus having to produce two chips instead of one.

The one historical case I know of where part-bad chips were successfully sold with reduced functionality is the 486, where units with a defective FPU were sold as the 486SX. Are there are any other cases?

If at all, only in the beginning. For most of their availability, 486SX were crippled on purpose to allow sales at lower prices without hurting the profits on 486DX sales.

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    Many people in the U.S., myself included, tended to judge the success or failure of Commodore's machines based upon sales in this country, even though a large portion of Commodore's target market was in Europe; I think the 16 and Plus/4 did better there than in the U.S.
    – supercat
    Aug 27, 2018 at 18:49
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    @supercat Thinking of it, I'm a bit puzzled about you comment, as my answer did nowere state anything about success or failure of either machine. All mentioned is the reasoning behind creating the C116 to counter the ZX machines at their price level and creating the C16 as 'real' machine (read no rubber keyboard) poitioned below the C64 but above the rubber keyboard class. Also, they where part of a biger strategy conceived before the gap closing C64 became the unexpected success it was. The Plus/4 was more of a last resort to use now surplus stock (and designs) made for the new line.
    – Raffzahn
    Aug 27, 2018 at 19:39
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    I was responding to your statement that the C16 wasn't a mistake, nor a bad idea, and wanted to acknowledge why some people might think it was: many people in the U.S. had no clue how popular various machines were in Europe.
    – supercat
    Aug 27, 2018 at 19:42
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    As I understand it, the 16 and Plus 4 did sell in significant numbers in Europe, but only after the price was reduced to the point where they were being sold at a loss, and customers who paid full price typically ended up unhappy at the lack of compatibility with the 64; for these reasons, both the engineers who built them and the company's management considered them mistakes, which is why I called them so.
    – rwallace
    Aug 28, 2018 at 21:18
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    @rwallace I guess we're down to semantics. A mistake is when you do something wrong, something you should have known better. Not realy the ace here. If at all, calling them a failure may be more apropriate, but as far as I know, the didn't sell at a loss, they made profit - they even has to do a second and third production run for the C16 to satisfy demand. I don't realy think this would have happened if it was sold at a loss, would it?
    – Raffzahn
    Aug 28, 2018 at 21:40

There was a brief fad in the early eighties for what's called "Wafer Scale Integration". That is to say, producing an entire wafer of silicon for a single circuit. The best known example was Gene Amdahl's Trilogy Systems. A Wafer Scale circuit can be used to build a massively powerful computer system in a single component, but as wafers are almost never produced without defects the concept relies on providing redundant units and being able to configure the system to use working ones and disable failed ones. The idea turned out to be too difficult to implement successfully, and AFAIK has never really been repeated, but a lot of research was put into it, and yielded some very good ways of testing wafers and disabling failed components.

Today, my understanding is that similar approaches are sometimes used with multicore processors: if you buy a two-core chip, it's entirely possible that what you actually get is a four-core chip with two of the cores disabled because they tested faulty.

  • This answer makes me wonder how system-on-a-chip designs compare to those Wafter Scale Integration designs...
    – user
    Aug 29, 2018 at 20:01
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    AMD's period of selling three-core processors was certainly based on failed quad-cores. Oct 5, 2018 at 21:02
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    @JohnDallman yes,it was - but it also just lasted for a few month, and then fully functional quad cores where disabled on purpose to deliver already placed orders for three-core ones, while no new orders where accepted. It#s been said that the net profit for AMD was low or even negative.
    – Raffzahn
    Mar 23, 2019 at 0:01
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    Another wafer-scale company (but maybe more hype than product) was Anamartic. Their Wafer Stack solid-state storage was the hot new thing briefly in 1989, but they were gone by 1992.
    – scruss
    Mar 23, 2019 at 21:30
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    Since this question popped up today, an update to this comment thread: in 2019 a company started producing wafer-scale AI chips. They draw 2 kW of power and are sold in dedicated servers.
    – jaskij
    Jan 18, 2020 at 16:50

This is the norm in the industry today. Both AMD and Intel manufacture all of their processor chips from a small number of wafer designs. If, for example, one or two of the cores on an 8 core die are faulty, then they disable those onboard and sell it as a 6 core chip. Same thing is done with faulty cache areas -- disabled and sold as a chip with less cache.

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    Similarly with hyperthreading, with flaws in the iGPU which might cause it to be sold as a chip without one or as one with fewer execution units, or with its ability to run at a particular clock rate which can result in it being sold as a particular SKU. In the case of GPUs there can be various defects that determine what model this chip can successfully be used for. This is completely ubiquitous in CPUs and GPUs where a manufacturer might have say 5 base chips which become 20 SKUs depending on exactly what defects they have.
    – Nye
    Jan 29, 2019 at 10:21

Intel very likely did this with surplus batches of ROM-equipped microcontrollers - eg if you look closely at the pinout of the 8031 vs 8051/8751, an 8051 wired up like an 8031 WILL behave as an 8031 no matter what is in the ROM/EPROM.

  • So you might've got a chip with someone else's proprietary code on it?
    – user253751
    Feb 13, 2020 at 14:36
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    You can run, but you can't unhide. Feb 13, 2020 at 18:44
  • It's ROM. Someone with sufficient business motivation could buy those chips and decap them and steal random other companies' trade secrets.
    – user253751
    Feb 14, 2020 at 12:11
  • @user253751: I have a suspicion that many companies would want to specify in their contracts that if they take delivery of an entire production run of mask ROM chips, Intel won't sell any chips with that code to anyone else. On the other hand, a company might want to initially take possession of part of a run, and then if they find that they have no need for the remainder, sell the balance (which never left Intel's possession) back to Intel at a discount, so as to recoup some of their cost.
    – supercat
    May 4, 2020 at 23:19
  • Possibly the technology to decap a ROM and read it out cold was considered out of reach of commercial users in the 1970s.... May 7, 2020 at 4:36

If you include FPGAs and flash memory (SSD chips), etc., many designs are (still?) manufactured with extra rows or blocks of stuff on the chip, were some number are expected to be disabled after failing (or too many passing?) device test, with the devices then still being sold under the same generic part number.

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    Flash chips don't have "extra" rows; instead, the manufacturer guarantees that a certain range of the chip will be free of bad rows, and the remainder will have at most a certain number, and those will read as zeroes unless or until they are erased, in which case which the factory would offer no guarantee about their behavior.
    – supercat
    Mar 19, 2019 at 17:19
  • A complete flash memory subsystem intended for a read/write filesystem - like an SSD on a chip - is very likely to have extra blocks to remap to. Also... are you sure NOR flash does not use extra rows, given it is expected to work without complex controllers as XIP memory? Feb 13, 2020 at 18:51
  • @rackandboneman: It's possible NOR flash has extra rows, but they're generally so much lower capacity than NAND flash that I wouldn't expect yields of perfect chips to be a problem. Are there any single-die SSD devices, or do they all combine a NAND flash die (with defective rows exposed as part of the addressing space) with a separate microcontroller die? Given the different process requirements for NAND flash and general CPU logic, I would think using separate dice would be more economical.
    – supercat
    Dec 15, 2020 at 6:17

Early versions of the MOS 6502 processor were sold with a faulty Rotate Right instruction; this instruction was simply left off the datasheet until a new batch of processors had been made.

Note that these chips were all bad because of a design error, as opposed to some bad chips due to yield issues.

  • That sounds like a potential nightmare with that type of instruction bring awol even if there are ways around it via other instructions. I am familiar with Z80 but not 6502 however a missing but expected inst must of been much erm "fun"
    – AndyF
    Jan 24, 2020 at 22:21
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    @AndyF The 6502 was a brand new chip at the time, so for early customers it was just a case of "oh, there isn't a Rotate Right instruction for this architecture" - it was missing a lot of other instructions you'd expect on a larger CPU die, but it was so much cheaper too! A fixed second batch was manufactured within months, and a revised instruction set published. The only lasting issue was that some early BASIC implementations etc. avoided using ROR in order to support machines with the first batch of chips. Subsequent new code used ROR whenever it was wanted.
    – Kaz
    Jan 26, 2020 at 4:56

Inmos (or perhaps Meiko) had a demo machine that used a large array of their parallel Transputer processors to solve dynamic finite-difference models in real time. They used Transputers that had failed internal memory testing but still had their inter-processor links working. This allowed a large array to be built at low cost, as the processors couldn't be sold with faulty memory but could be used as calculation nodes. I remember seeing a demo of the machine animate the waves in a snare drum head in real time. This was a huge deal in the 1980s.

Of course, I can't find documentary proof of this. It may have been shown on Tomorrow's World. There's very little left in computing history about Inmos. Their longest-lasting legacy was in VGA's slightly unusual colour choice. IBM chose an Inmos RAMDAC for the first VGA cards, and its specific timing resulted in the old and familiar VGA palette.

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